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1 typical a pplica t ion fea t ures descrip t ion dual 13a or single 26a module regulator with digital power system management the lt m ? 4676 is a dual 13 a or single 26 a step-down umodule ? ( micromodule) dc/dc regulator featuring re- mote configurability and telemetry-monitoring of power management parameters over pmbus an open standard i 2 c-based digital interface protocol . the LTM4676 is comprised of fast analog control loops, precision mixed- signal circuitry, eeprom, power mosfets, inductors and supporting components. the LTM4676s 2- wire serial interface allows outputs to be margined, tuned and ramped up and down at programmable slew rates with sequencing delay times. input and output currents and voltages, output power, temperatures, uptime and peak values are readable. custom configuration of the eeprom contents is not required. at start-up, output voltages, switching frequency, and channel phase angle assignments can be set by pin-strapping resistors. the ltpowerplay ? gui and dc1613 usb - to- pmbus converter and demo kits are available. the LTM4676 is offered in a 16mm 16mm 5.01mm bga package available with snpb or rohs compliant terminal finish. a pplica t ions n dual, fast, analog loops with digital interface for control and monitoring n wide input voltage range : 4.5 v to 26.5v n output voltage range : 0.5 v to 5.4v (4 v on v out0 ) n 1% maximum dc output error over temperature n 2.5% current readback accuracy at 10 a load n 400 khz pmbus-compliant i 2 c serial interface n integrated 16- bit ? adc n constant frequency current mode control n parallel and current share multiple modules n 16 slave addresses; rail/global addressing n 16mm 16 mm 5.01 mm bga package readable data: n input and output voltages, currents, and temperatures n running peak values, uptime, faults and warnings n onboard eeprom fault log record writable data and configurable parameters: n output voltage, voltage sequencing and margining n digital soft-start/stop ramp n ov/uv/ot, uvlo, frequency and phasing n system optimization, characterization and data min- ing in prototype, production and field environments n telecom, datacom, and storage systems l, lt , lt c , lt m , linear technology, the linear logo, module, burst mode and polyphase are registered trademarks and ltpowerplay is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 7420359, 8163643. licensed under u.s. patent 7000125 and other related patents worldwide. dual 13a module regulator with digital interface for control and monitoring* using pmbus and ltpowerplay to monitor telemetry and margin v out0 /v out1 during load pattern tests. 10hz polling rate. 12v in 22f 3 on/off control fault interrupts, power sequencing pwm clock and time-base synchronization v in 5.75v to 26.5v v osns0 ? v out0 , adjustable up to 13a 100f 7 v osns0 + v out0 v in0 v in1 sv in load 0 v out1 , adjustable up to 13a 100f 7 i 2 c/smbus i/f with pmbus command set to/from ipmi or other board management controller load 1 run 0 run 1 wp *for complete circuit, see figure 44 LTM4676 gnd 4676 ta01a sgnd scl sda alert v osns1 v out1 gpio 0 gpio 1 register write protection sync share_clk 1.1 1.0 0.9 v out0 (v) v out1 (v) 0.8 1.9 1.8 1.7 1.6 0 3 6 time (sec) output voltage readback, v out margined 7.5% low 4677 ta01b 9 12 15 10 5 i out0 (a) i out1 (a) 0 15 10 5 0 0 3 6 time (sec) output current readback, varying load pattern 4676 ta01c 9 12 1.5 1.0 0.5 i in0 (a) i in1 (a) 0 2.4 1.6 0.8 0 0 3 6 time (sec) input current readback 4676 ta01d 9 12 60 57 54 channel 0 temp (c) channel 1 temp (c) 51 60 57 54 51 0 3 6 time (sec) power stage temperature readback 4676 ta01e 9 12 click to view associated techclip videos. 4676fb for more information www.linear.com/LTM4676 ltm 4676
2 table o f c on t en t s features ..................................................... 1 applications ................................................ 1 t ypical application ........................................ 1 description .................................................. 1 absolute maximum ratings .............................. 3 order information .......................................... 3 pin configuration .......................................... 3 electrical characteristics ................................. 4 t ypical performance characteristics .................. 11 pin functions .............................................. 14 simplified block diagram ............................... 19 decoupling requirements ............................... 19 functional diagram ...................................... 20 t est circuits ............................................... 21 operation ................................................... 22 power module introduction .................................... 22 p ower module configurability and readback data ........................................................ 24 ti me-averaged and peak readback data ................ 26 p ower module overview ......................................... 29 e eprom ................................................................. 33 add itional information ............................................ 33 applications information ................................ 34 l tm4676 control ic differences from ltc3880 ..... 34 v in to v out step-down ratios ................................ 45 in put capacitors ..................................................... 45 o utput capacitors ................................................... 45 l ight load current operation ................................. 45 s witching frequency and phase ............................. 46 mi nimum on-time considerations .......................... 48 variable delay time, soft-start and output voltage ramping ................................................................. 48 d igital servo mode ................................................. 49 s oft off (sequenced off) ........................................ 50 u ndervoltage lockout ............................................. 50 f ault conditions ...................................................... 51 o pen-drain pins ..................................................... 51 p hase-locked loop and frequency synchronization ...................................................... 52 r config pin-straps (external resistor configuration pins) ................................................. 52 v oltage selection .................................................... 52 co nnecting the usb to the i 2 c/smbus/pmbus controller to the LTM4676 in system ..................... 53 l tpowerplay: an interactive gui for digital power system management .............................................. 54 p mbus communication and command processing .............................................................. 56 t hermal considerations and output current derating ......................................... 58 e mi performance .................................................... 66 s afety considerations ............................................. 67 l ayout checklist/example ...................................... 67 typical applications ...................................... 68 package description ..................................... 74 package photograph ..................................... 75 package description ..................................... 76 revision history .......................................... 77 t ypical application ....................................... 78 design resources ........................................ 78 related parts .............................................. 78 the ltc3880 data sheet is an essential reference document for this product. to obtain it go to: www.linear.com/ltc3880 4676fb for more information www.linear.com/LTM4676 ltm 4676
3 p in c on f igura t ion a bsolu t e maxi m u m r a t ings terminal voltages : v in n ( note 4), sv in ..................................... C0. 3 v to 28 v v out n ........................................................... C0. 3 v to 6v v osns 0 + , v orb 0 + ..................................... C0. 3 v to 4.25 v v osns1 , v orb1 , intv cc , i snsn a + , i snsn b + , i sns n a C , i sns n b C ........................................... C0. 3 v to 6v run n , sda , scl , alert ........................... C 0.3 v to 5.5 v f swphcfg , v out n cfg , v trim n cfg , asel .. C 0.3 v to 2.75 v v dd 33 , gpio n , sync , share _ clk , wp , tsns n a , comp n a , comp n b , v osns 0 C , v orb 0 C ......... C0.3 v to 3.6 v sgnd ........................................................ C 0.3 v to 0.3 v terminal currents intv cc peak output current ................................ 10 0 ma v dd 25 ................................................... C1. 5 ma to 1.5 ma tsns n b .................................................... C1 ma to 10 ma t emperatures internal operating temperature range ( notes 2, 3) ............................................ C 40 c to 125 c storage temperature range .................. C 55 c to 125 c peak package body temperature during reflow .. 245 c (note 1) v in0 v in1 v out0 v out1 1 a b c d e f g h j k l m 2 3 4 5 6 7 top view 8 9 10 11 12 gnd gnd gnd gnd bga package 144-lead (16mm 16mm 5.01mm) gnd gnd t jmax = 125c, jctop = 8.8c/w, jcbottom = 0.8c/w, jb = 1.3c/w, ja = 10.3c/w values determined per jesd51-12 weight = 3.3 grams o r d er i n f or m a t ion part number pad or ball finish part marking* package type msl ra ting temperature range (note 2) device finish code LTM4676ey#pbf sac305 (rohs) LTM4676y e1 bga 4 C40c to 125c LTM4676iy#pbf sac305 (rohs) LTM4676y e1 bga 4 C40c to 125c LTM4676iy snpb (63/37) LTM4676y e0 bga 4 C40c to 125c consult marketing for parts specified with wider operating temperature ranges. *device temperature grade is indicated by a label on the shipping container. pad or ball finish code is per ipc/jedec j-std-609. ? terminal finish part marking: www.linear.com/leadfree ? recommended lga and bga pcb assembly and manufacturing procedures: www.linear.com/umodule/pcbassembly ? lga and bga package and t ray drawings: www.linear.com/packaging 4676fb for more information www.linear.com/LTM4676 ltm 4676
4 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified internal operating temperature range ( note 2). specified as each individual output channel ( note 4). t a = 25c , v in = 12v , run n = 5 v, frequency_ switch = 500khz and v outn commanded to 1.000 v unless otherwise noted. configured with factory- default eeprom settings and per test circuit 1, unless otherwise noted. symbol parameter conditions min typ max units v in input dc voltage test circuit 1 test circuit 2; vin_off < vin_on = 4.25v l l 5.75 4.5 26.5 5.75 v v v out0 range of output voltage regulation, channel 0 v out0 differentially sensed on v osns0 + /v osns0 C pin-pair; commanded by serial bus or with resistors present at start-up on v out0cfg and/or v trim0cfg l 0.5 4.0 v v out1 range of output voltage regulation, channel 1 v out1 differentially sensed on v osns1 /sgnd pin-pair; commanded by serial bus or with resistors present at start-up on v out1cfg and/ or v trim1cfg l 0.5 5.4 v v outn (dc) output voltage, total variation with line and load digital servo engaged (mfr_pwm_mode n [6] = 1 b ) digital servo disengaged (mfr_pwm_mode n [6] = 0 b ) v outn commanded to 1.000v, v outn low range (mfr_pwm_config[6-n] = 1 b ), frequency_switch = 250khz (note 5) l 0.990 0.985 1.000 1.000 1.010 1.015 v v input specifications i inrush(vin) input inrush current at start-up test circuit 1, v outn =1v, v in = 12v; no load besides capacitors; ton_rise n = 3ms 400 ma i q(svin) input supply bias current forced continuous mode, mfr_pwm_mode n [1:0] = 10 b run n = 5v, run 1-n = 0v shutdown, run 0 = run 1 = 0v 40 20 ma ma i s(vinn,burst) input supply current in burst mode ? operation burst mode operation, mfr_pwm_mode n [1:0] = 01 b , i outn = 100ma 15 ma i s(vinn,psm) input supply current in pulse-skipping mode operation pulse-skipping mode, mfr_pwm_mode n [1:0] = 00 b , i outn = 100ma 20 ma i s(vinn,fcm) input supply current in forced-continuous mode operation forced continuous mode, mfr_pwm_mode n [1:0] = 10 b i outn = 100ma i outn = 13a 40 1.37 ma a i s(vinn,shutdown) input supply current in shutdown shutdown, run n = 0v 50 a output specifications i outn output continuous current range (note 6) 0 13 a ?v outn(line) v outn line regulation accuracy digital servo engaged (mfr_pwm_mode n [6] = 1 b ) digital servo disengaged (mfr_pwm_mode n [6] = 0 b ) sv in and v inn electrically shorted together and intv cc open circuit; i outn = 0a, 5.75v v in 26.5v, v out low range (mfr_pwm_config[6-n] = 1 b ) frequency_switch = 250khz (referenced to 12v in ) (note 5) l 0.03 0.03 0.2 % %/v ?v outn(load) v outn load regulation accuracy digital servo engaged (mfr_pwm_mode n [6] = 1 b ) digital servo disengaged (mfr_pwm_mode n [6] = 0 b ) 0a i outn 13a, v out low range, (mfr_pwm_config[6-n] = 1 b ) frequency_switch = 250khz (note 5) l 0.03 0.2 0.5 % % v outn(ac) output voltage ripple 10 mv p-p f s (each channel) v outn ripple frequency frequency_switch set to 500khz (0xfbe8) l 462.5 500 537.5 khz ?v outn (start) turn-on overshoot ton_rise n = 3ms (note 12) 8 mv t start turn-on start-up time time from v in toggling from 0v to 12v to rising edge of gpio n . ton_delay n = 0ms, ton_rise n = 3ms, mfr_gpio_propagate n = 0x0100, mfr_gpio_response n = 0x0000 l 153 170 ms 4676fb for more information www.linear.com/LTM4676 ltm 4676
5 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified internal operating temperature range ( note 2). specified as each individual output channel ( note 4). t a = 25c , v in = 12v , run n = 5 v, frequency_ switch = 500khz and v outn commanded to 1.000 v unless otherwise noted. configured with factory- default eeprom settings and per test circuit 1, unless otherwise noted. symbol parameter conditions min typ max units t delay(0ms) turn-on delay time time from first rising edge of run n to rising edge of gpio n . ton_delay n = 0ms, ton_rise n = 3ms, mfr_gpio_propagate n = 0x0100, mfr_gpio_response n = 0x0000. v in having been established for at least 170ms l 2.75 3.1 3.5 ms ?v outn (ls) peak output voltage deviation for dynamic load step load: 0a to 6.5a and 6.5a to 0a at 6.5a/s, figure 44 circuit, v outn = 1v, v in = 12v (note 12) 50 mv t settle settling time for dynamic load step load: 0a to 6.5a and 6.5a to 0a at 6.5a/s, figure 44 circuit, v outn = 1v, v in = 12v (note 12) 35 s i outn(ocl_pk) output current limit, peak cycle-by-cycle inductor peak current limit inception 22.5 a i outn(ocl_ avg ) output current limit, time averaged time-averaged output inductor current limit inception threshold, commanded by iout_oc_fault_limit n (note 12) 15.6a; see i o-rb-acc specification (output current readback accuracy) control section v fbcm0 channel 0 feedback input common mode range v osns0 C valid input range (referred to sgnd) v osns0 + valid input range (referred to sgnd) l l C0.1 0.3 4.25 v v v fbcm1 channel 1 feedback input common mode range sgnd v alid input range (referred to gnd) v osns1 valid input range (referred to sgnd) l l C0.3 0.3 5.5 v v v out0-rng0 channel 0 full-scale command voltage, range 0 (notes 7, 15) v out0 commanded to 4.095v, mfr_pwm_config[6] = 0 b resolution lsb step size 4.015 12 1.375 4.176 v bits mv v out0-rng1 channel 0 full-scale command voltage, range 1 (notes 7, 15) v out0 commanded to 2.750v, mfr_pwm_config[6] = 1 b resolution lsb step size 2.711 12 0.6875 2.788 v bits mv v out1-rng0 channel 1 full-scale command voltage, range 0 (notes 7, 15) v out1 commanded to 5.500v, mfr_pwm_config[5] = 0 b resolution lsb step size 5.422 12 1.375 5.576 v bits mv v out1-rng1 channel 1 full-scale command voltage, range 1 (notes 7, 15) v out1 commanded to 2.750v, mfr_pwm_config[5] = 1 b resolution lsb step size 2.711 12 0.6875 2.788 v bits mv r vsense0 + v osns0 + impedance to sgnd 0.05v v vosns0 + C v sgnd 4.1v 41 k r vsense1 v osns1 impedance to sgnd 0.05v v vosns1 C v sgnd 5.5v 37 k t on(min) minimum on-time (note 8 ) 90 ns analog ov/ uv ( overvoltage/ undervoltage) output voltage supervisor comparators ( vout_ ov/ uv_ fault_ limit and vout_ ov/ uv_ warn_ limit monitors) n ov/uv_comp resolution, output voltage supervisors, channels 0 and 1 (note 15) 8 bits v0 ou-rng output voltage comparator threshold detection range, channel 0 ( note 15) high range scale, mfr_pwm_config[6] = 0 b low range scale, mfr_pwm_config[6] = 1 b 1 0.5 4.095 2.7 v v 4676fb for more information www.linear.com/LTM4676 ltm 4676
6 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified internal operating temperature range ( note 2). specified as each individual output channel ( note 4). t a = 25c , v in = 12v , run n = 5 v, frequency_ switch = 500khz and v outn commanded to 1.000 v unless otherwise noted. configured with factory- default eeprom settings and per test circuit 1, unless otherwise noted. symbol parameter conditions min typ max units v0 ou-stp output voltage comparator threshold programming lsb step size, channel 0 (note 15) high range scale, mfr_pwm_config[6] = 0 b low range scale, mfr_pwm_config[6] = 1 b 22 11 mv mv v 0 ou-acc output voltage comparator threshold accuracy, channel 0 (see note 14) 2v v vosns0 + C v vosns0 C 4.095v, mfr_pwm_config[6] = 0 b 1v v vosns0 + C v vosns0 C 2.7v, mfr_pwm_config[6] = 1 b 0.5v v vosns0 + C v vosns0 C < 1v, mfr_pwm_config[6] = 1 b l l l 2 2 20 % % mv v 1 ou-rng output voltage comparator threshold detection range, channel 1 ( note 15) high range scale, mfr_pwm_config[5] = 0 b low range scale, mfr_pwm_config[5] = 1 b 1 0.5 5.5 2.7 v v v 1 ou-stp output voltage comparator threshold programming lsb step size, channel 1 (note 15) high range scale, mfr_pwm_config[5] = 0 b low range scale, mfr_pwm_config[5] = 1 b 22 11 mv mv v 1 ou-acc output voltage comparator threshold accuracy, channel 1 (see note 14) 2v v vosns1 C v sgnd 5.5v, mfr_pwm_config[5] = 0 b 1.5v v vosns1 C v sgnd 2.7v, mfr_pwm_config[5] = 1 b 0.5v v vosns1 C v sgnd < 1.5v, mfr_pwm_config[5] = 1 b l l l 2 2 30 % % mv t prop-ov output ov comparator response times, channels 0 and 1 overdrive to 10% above programmed threshold 35 s t prop-uv output uv comparator response times, channels 0 and 1 underdrive to 10% below programmed threshold 50 s analog ov/uv sv in input voltage supervisor comparators (threshold detectors for vin_on and vin_off) n svin-ov/uv-comp sv in ov/uv comparator threshold-programming resolution (note 15) 8 bits sv in-ou-range sv in ov/uv comparator threshold-programming range l 4.5 20 v sv in-ou-stp sv in ov/uv comparator threshold-programming lsb step size (note 15) 82 mv sv in-ou-acc sv in ov/uv comparator threshold accuracy 9v < sv in 20v 4.5v sv in 9v l l 2.5 225 % mv t prop- svin- high- vin sv in ov/uv comparator response time, high v in operating configuration test circuit 1, and: vin_on = 9v; sv in driven from 8.775v to 9.225v vin_off = 9v; sv in driven from 9.225v to 8.775v l l 35 35 s s t prop-svin-low-vin sv in ov/uv comparator response time, low v in operating configuration test circuit 2, and: vin_on = 4.5v; sv in driven from 4.225v to 4.725v vin_off = 4.5v; sv in driven from 4.725v to 4.225v l l 35 35 s s channels 0 and 1 output voltage readback (read_vout n ) n vo-rb output voltage readback resolution and lsb step size (note 15) 16 244 bits v 4676fb for more information www.linear.com/LTM4676 ltm 4676
7 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified internal operating temperature range ( note 2). specified as each individual output channel ( note 4). t a = 25c , v in = 12v , run n = 5 v, frequency_ switch = 500khz and v outn commanded to 1.000 v unless otherwise noted. configured with factory- default eeprom settings and per test circuit 1, unless otherwise noted. symbol parameter conditions min typ max units v o-f/s output voltage full-scale digitizable range v runn = 0v (notes 7, 15) 8 v v o-rb-acc output voltage readback accuracy channel 0: 0.6v v vosns0 + C v vosns0 C 4v channel 1: 0.6v v vosns1 C v sgnd 5.4v l l within 1% of reading within 1% of reading t convert-vo-rb output voltage readback update rate (notes 9, 15) 100 ms input voltage (sv in ) readback (read_vin) n svin-rb input voltage readback resolution and lsb step size (notes 10, 15) 10 15.625 bits mv sv in-f/s input voltage full-scale digitizable range (notes 11, 15) 38.91 v sv in-rb-acc input voltage readback accuracy read_vin, 4.5v sv in 26.5v l within 2% of reading t convert-svin-rb input voltage readback update rate (notes 9, 15) 100 ms channels 0 and 1 output current ( read_ iout n ), duty cycle ( read_ duty_ cycle n ), and computed input current ( mfr_ read_ iin n ) readback n io-rb output current readback resolution and lsb step size (notes 10, 12) 10 15.6 bits ma i o-f/s , i i-f/s output current full-scale digitizable range and input current range of calculation (note 12) 40 a i o-rb-acc output current, readback accuracy read_iout n , channels 0 and 1, 0 i outn 10a, forced-continuous mode, mfr_pwm_mode n [1:0] = 10 b l within 250ma of reading i o-rb(13a) full load output current readback i outn = 13a (note 12). see histograms in typical performance characteristics 13.1 a n ii-rb computed input current, readback resolution and lsb step size (notes 10, 12) 10 1.95 bits ma i i-rb-acc computed input current, readback accuracy, neglecting i svin mfr_read_iin n , channels 0 and 1, 0 i outn 10a, forced-continuous mode, mfr_pwm_mode n [1:0] = 10 b , mfr_iin_offset n = 0ma l within 150 ma of reading t convert-io-rb output current readback update rate (notes 9, 15) 100 ms t convert-ii-rb computed input current, readback update rate (notes 9, 15) 100 ms n duty-rb resolution, duty cycle readback (notes 10, 15) 10 bits d rb-acc duty cycle tue read_duty-cycle n , 16.3% duty cycle (note 15) 3 % t convert-duty-rb duty cycle readback update rate (notes 9, 15) 100 ms temperature readback for channel 0, channel 1, and controller (respectively: read_temperature_1 0 , read_temperature_1 1 , and read_temperature_2) t res-rb temperature readback resolution channel 0, channel 1, and controller (note 15) 0.0625 c 4676fb for more information www.linear.com/LTM4676 ltm 4676
8 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified internal operating temperature range ( note 2). specified as each individual output channel ( note 4). t a = 25c , v in = 12v , run n = 5 v, frequency_ switch = 500khz and v outn commanded to 1.000 v unless otherwise noted. configured with factory- default eeprom settings and per test circuit 1, unless otherwise noted. symbol parameter conditions min typ max units t rb-ch-acc(72mv) channel temperature tue, switching action off channels 0 and 1, pwm inactive, run n = 0v, ?v tsnsna = 72mv l within 3c of reading t rb-ch-acc(on) channel temperature tue, switching action on read_temperature_1 n , channels 0 and 1, pwm active, run n = 5v (note 12) within 3c of reading t rb-ctrl-acc(on) control ic die temperature tue, switching action on read_temperature_2, pwm active, run 0 = run 1 = 5v (note 12) within 1c of reading t convert-temp-rb temperature readback update rate ( notes 9, 15) 100 ms int v cc regulator v intvcc internal v cc voltage no load 6v v in 26.5v l 4.8 5 5.2 v ?v intvcc(load) v intvcc intv cc load regulation 0ma i intvcc 50ma 0.5 2 % v dd33 regulator v vdd33 internal v dd33 voltage l 3.2 3.3 3.4 v i lim(vdd33) v dd33 current limit v dd33 electrically short-circuited to gnd 70 ma v vdd33_ov v dd33 overvoltage threshold (note 15) 3.5 v v vdd33_uv v dd33 undervoltage threshold (note 15) 3.1 v v dd25 regulator v vdd25 internal v dd25 voltage l 2.25 2.5 2.75 v i lim(vdd25) v dd25 current limit v dd25 electrically short-circuited to gnd 50 ma oscillator and phase-locked loop (pll) f osc oscillator frequency accuracy frequency_switch = 500khz (0xfbe8) 250khz frequency_switch 1mhz (note 15) l 7.5 7.5 % % f sync pll sync capture range frequency_switch set to frequency slave mode (0x0000); sync driven by external clock; 3.3v out l 225 1100 khz v th,sync sync input threshold v sync rising (note 15) v sync falling (note 15) 1.5 1 v v v ol,sync sync low output voltage i sync = 3ma l 0.3 0.4 v i sync sync leakage current in frequency slave mode 0v v sync 3.6v frequency_switch set to slave mode (0x0000) l 5 a sync -0 sync-to-channel 0 phase relationship, lag from falling edge of sync to rising edge of top mosfet (mt0) gate (note 15) mfr_pwm_config[2:0] = 000 b , 01x b mfr_pwm_config[2:0] = 101 b mfr_pwm_config[2:0] = 001 b mfr_pwm_config[2:0] = 1x0 b 0 60 90 120 deg deg deg deg sync -1 sync-to-channel 1 phase relationship, lag from falling edge of sync to rising edge of top mosfet (mt1) gate (note 15) mfr_pwm_config[2:0] = 011 b mfr_pwm_config[2:0] = 000 b mfr_pwm_config[2:0] = 010 b , 10x b mfr_pwm_config[2:0] = 001 b mfr_pwm_config[2:0] = 110 b 120 180 240 270 300 deg deg deg deg deg 4676fb for more information www.linear.com/LTM4676 ltm 4676
9 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified internal operating temperature range ( note 2). specified as each individual output channel ( note 4). t a = 25c , v in = 12v , run n = 5 v, frequency_ switch = 500khz and v outn commanded to 1.000 v unless otherwise noted. configured with factory- default eeprom settings and per test circuit 1, unless otherwise noted. symbol parameter conditions min typ max units eeprom characteristics endurance (note 13) 0c t j 85c during eeprom write operations (note 3) l 10,000 cycles retention (note 13) t j < t j(max) , with most recent eeprom write operation having occurred at 0c t j 85c (note 3) l 10 years mass_write mass write operation time execution of store_user_all command, 0c t j 85c ( ate - tested at t j = 25c) (notes 3, 13) 440 4100 ms digital i/os v ih input high threshold voltage scl, sda, run n , gpio n (note 15) share_clk, wp (note 15) 2.0 1.8 v v v il input low threshold voltage scl, sda, run n , gpio n (note 15) share_clk, wp (note 15) 1.4 0.6 v v v hyst input hysteresis scl, sda (note 15) 80 mv v ol output low voltage scl, sda, alert, run n , gpio n , share_clk: i sink = 3ma l 0.3 0.4 v i ol input leakage current sda, scl, alert , run n : 0v v pin 5.5v gpio n and share_clk: 0v v pin 3.6v l l 5 2 a a t filter input digital filtering run n (note 15) gpio n (note 15) 10 3 s s c pin input capacitance scl, sda, run n , gpio n , share_clk, wp (note 15) 10 pf pmbus interface timing characteristics f smb serial bus operating frequency (note 15) 10 400 khz t buf bus free time between stop and start (note 15) 1.3 s t hd, sta hold time after repeated start condition time period after which first clock is generated (note 15) 0.6 s t su, sta repeated start condition setup time (note 15) 0.6 s t su,sto stop condition setup time (note 15) 0.6 s t hd, dat data hold time receiving data (note 15) transmitting data (note 15) 0 0.3 0.9 s s t su, dat data setup time receiving data (note 15) 0.1 s t timeout_smb stuck pmbus timer timeout measured from the last pmbus start event: block reads (note 15) non-block reads (note 15) 150 32 ms ms t low serial clock low period (note 15) 1.3 10000 s t high serial clock high period (note 15) 0.6 s note 1: stresses beyond those listing under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime. note 2: the LTM4676 is tested under pulsed-load conditions such that t j t a . the LTM4676e is guaranteed to meet performance specifications over the 0c to 125c internal operating temperature range. specifications over the C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the LTM4676i is guaranteed to meet specifications over the full C40c to 125 c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. 4676fb for more information www.linear.com/LTM4676 ltm 4676
10 e lec t rical c harac t eris t ics note 3: the LTM4676s eeprom temperature range for valid write commands is 0c to 85c. to achieve guaranteed eeprom data retention, execution of the store_user_all commandi.e., uploading ram contents to nvmoutside this temperature range is not recommended. however, as long as the LTM4676s eeprom temperature is less than 130c, the LTM4676 will obey the store_user_all command. only when eeprom temperature exceeds 130c, the LTM4676 will not act on any store_user_all transactions: instead, the LTM4676 nacks the serial command and asserts its relevant cml (communications, memory, logic) fault bits. eeprom temperature can be queried prior to commanding store_user_all; see the applications information section. note 4: the two power inputsv in0 and v in1 and their respective power outputsv out0 and v out1 are tested independently in production. a shorthand notation is used in this document that allows these parameters to be refered to by v inn and v outn , where n is permitted to take on a value of 0 or 1. this italicized, subscripted n notation and convention is extended to encompass all such pin names, as well as register names with channel-specific, i.e., paged data. for example, vout_command n refers to the vout_command command code data located in pages 0 and?1, which in turn relate to channels 0 (v out0 ) and channel 1 (v out1 ). registers containing non-page-specific data, i.e., whose data is global to the module or applies to both of the module's channels lack the italicized, subscripted n , e.g., frequency_switch. note 5: v outn (dc) and line and load regulation tests are performed in production with digital servo disengaged (mfr_pwm_mode n [6]?=?0 b ) and low v outn range selected (mfr_pwm_config[6-n ] = 1 b . the digital servo control loop is exercised in production (setting mfr_pwm_ mode n [6] = 1 b ), but convergence of the output voltage to its final settling value is not necessarily observed in final testdue to potentially long time constants involvedand is instead guaranteed by the output voltage readback accuracy specification. evaluation in application demonstrates capability; see the typical performance characteristics section. note 6: see output current derating curves for different v in , v out , and t a , located in the applications information section. note 7: even though v out0 and v out1 and their associated current- sensing pins (i snsn [a/b][+/C] ) are specified for 6v absolute maximum and recommended for not more than 5.5v continuous, the maximum recommended command voltage to regulate output channels 0 and 1 is: 4.0v and 5.4v, respectively, when the v out range setting for those channelsmfr_pwm_configs bits 6 and 5, respectivelyare set to high range, i.e., 0 b ; and 2.5v for any channel whose respective mfr_pwm_config v out range-setting bit is set to low range, i.e., 1 b . note 8: minimum on-time is tested at wafer sort. note 9: data conversion is performed in round-robin (cyclic) fashion. all telemetry signals are continuously digitized, and reported data is based on measurements not older than 100ms, typical. note 10: the following telemetry parameters are formatted in pmbus- defined linear data format, in which each register contains a word comprised of 5 most significant bitsrepresenting a signed exponent, to be raised to the power of 2and 11 least significant bitsrepresenting a signed mantissa: input voltage (on sv in ), accessed via the read_vin command code; output currents (i outn ), accessed via the read_iout n command codes; module input current (i vin0 + i vin1 + i svin ), accessed via the read_iin command code; channel input currents (i vinn + 1/2 ? i svin ), accessed via the mfr_read_iin n command codes;and duty cycles of channel 0 and channel 1 switching power stages, accessed via the read_duty_cycle n command codes. this data format limits the resolution of telemetry readback data to 10 bits even though the internal adc is 16 bits and the LTM4676s internal calculations use 32-bit words. note 11: the absolute maximum rating for the sv in pin is 28v. input voltage telemetry (read_vin) is obtained by digitizing a voltage scaled down from the sv in pin. note 12: these typical parameters are based on bench measurements and are not production tested. note 13: eeprom endurance and retention are guaranteed by wafer-level testing for data retention. the minimum retention specification applies for devices whose eeprom has been cycled less than the minimum endurance specification, and whose eeprom data was written to at 0c t j 85c. the restore_user_all command (downloading nvm contents to ram) is valid over the entire operating temperature range and does not influence eeprom characteristics. note 14: v0 ou-acc ov/uv comparator threshold accuracy for mfr_pwm_config[6] = 1 b tested in ate at v vosns0 + C v vosns0 C = 0.5v and 2.7v. 1v condition tested at ic-level, only. v1 ou-acc ov/uv comparator threshold accuracy for mfr_pwm_config[5] = 1 b tested in ate with v vosns1 -v sgnd = 0.5v and 2.7v. 1.5v condition tested at ic-level, only. note 15: tested at ic-level ate . 4676fb for more information www.linear.com/LTM4676 ltm 4676
11 typical p er f or m ance c harac t eris t ics efficiency vs output current, 5v in , v out0 and v out1 paralleled, v in = sv in = v inn = intv cc , mfr_pwr_mode n [1:0] = 10 b efficiency vs output current, v out1 = 5v, v out0 = off, v in = sv in = v inn , intv cc open, mfr_pwr_mode n [1:0] = 10 b efficiency vs output current, 24v in , v out0 and v out1 paralleled, v in = sv in = v inn , intv cc open, mfr_pwr_mode n [1:0] = 10 b efficiency vs output current, 8v in , v out0 and v out1 paralleled, v in = sv in = v inn , intv cc open, mfr_pwr_mode n [1:0] = 10 b single phase single output burst mode efficiency, v in = sv in = v inn , intv cc open, mfr_pwr_mode n [1:0] = 01 b efficiency vs output current, 12v in , v out0 and v out1 paralleled, v in = sv in = v inn , intv cc open, mfr_pwr_mode n [1:0] = 10 b t a = 25c, 12v in to 1v out , unless otherwise noted. output current (a) 0 2 4 80 90 22 24 26 4676 g01 70 60 6 8 10 12 14 16 18 20 100 75 85 65 95 3.3v out , 425khz 2.5v out , 425khz 1.8v out , 425khz 1.5v out , 350khz 1.2v out , 350khz 1.0v out , 350khz 0.9v out , 350khz efficiency (%) output current (a) 0 2 4 80 90 22 24 26 4676 g02 70 60 6 8 10 12 14 16 18 20 100 75 85 65 95 3.3v out , 575khz 2.5v out , 500khz 1.8v out , 425khz 1.5v out , 350khz 1.2v out , 350khz 1.0v out , 350khz 0.9v out , 350khz efficiency (%) output current (a) 0 2 4 80 90 22 24 26 4676 g03 70 60 6 8 10 12 14 16 18 20 100 75 85 65 95 3.3v out , 650khz 2.5v out , 575khz 1.8v out , 500khz 1.5v out , 425khz 1.2v out , 350khz 1.0v out , 350khz 0.9v out , 350khz efficiency (%) output current (a) 0 2 4 80 90 22 24 26 4676 g04 70 60 6 8 10 12 14 16 18 20 100 75 85 65 95 3.3v out , 750khz 2.5v out , 650khz 1.8v out , 500khz 1.5v out , 425khz 1.2v out , 350khz 1.0v out , 250khz 0.9v out , 250khz efficiency (%) output current (a) 0 1 2 80 90 11 12 13 4676 g05 70 60 3 4 5 6 7 8 9 10 100 75 85 65 95 8v in , 500khz 12v in , 750khz 24v out , 1mhz efficiency (%) output current (a) 0 1 2 50 70 11 12 13 4676 g06 40 3 4 5 6 7 8 9 10 90 60 80 24v in to 5v out , 1mhz 12v in to 1.5v out , 425khz efficiency (%) 4676fb for more information www.linear.com/LTM4676 ltm 4676
12 typical p er f or m ance c harac t eris t ics t a = 25c, 12v in to 1v out , unless otherwise noted. dual phase single output?load transient response,12v in to 1v out single phase single output?load transient response,12v in to 1v out dual phase single output?load transient response, 5v in to 1v out dual output concurrent rail start-up/shutdown dual output start-up/shutdown with a pre-biased load single phase single output? short-circuit protection at no load single phase single output?load transient response, 24v in to 1v out single phase single output?load transient response, 24v in to 3.3v out single phase single output pulse-skipping (discontinuous) mode efficiency, v in = sv in = v inn , intv cc open, mfr_pwr_mode n [1:0] = 00 b output current (a) 0 1 2 50 70 11 12 13 4676 g07 40 3 4 5 6 7 8 9 10 90 60 80 24v in to 5v out , 1mhz 12v in to 1.5v out , 425khz efficiency (%) v out 50mv/div ac-coupled i out 8a/div 40s/div figure 35 circuit at 12v in , intv cc pin open circuit and vout_command n set to 1.000v. 0a to 20a load step at 20a/s 4676 g08 v out0 50mv/div ac-coupled i out 4a/div 40s/div figure 44 circuit at 12v in 0a to 10a load step at 10a/s 4676 g09 v out 50mv/div ac-coupled i out 8a/div 40s/div figure 35 circuit at 5v in , vout_command n set to 1.000v. 0a to 20a load step at 20a/s 4676 g10 v out0 50mv/div ac-coupled i out 4a/div 40s/div figure 44 circuit at 24v in 0a to 10a load step at 10a/s 4676 g11 v out0 50mv/div ac-coupled i out 4a/div 40s/div figure 44 circuit at 24v in , c out0 = 5 100f and v out0 commanded to 3.300v. 0a to 10a load step at 10a/s 4676 g12 v out0 , v out1 500mv/div i out0 5a/div run 0 , run 1 5v/div 2ms/div figure 44 circuit at 12v in , 77m load on v out0 , no load on v out1 . ton_rise 0 = 3ms, ton_rise 1 = 5.297ms, toff_delay 1 = 0ms, toff_delay 0 = 2.43ms, toff_fall 1 = 5.328ms, toff_fall 0 = 3ms, on_off_config n = 0x1e 4676 g13 v out0 , v out1 500mv/div i diode 1ma/div run 0 , run 1 5v/div 2ms/div figure 44 circuit at 12v in , 77m load on v out0 , 500 on v out1 . v out1 pre-biased through a diode. ton_rise 0 = 3ms, ton_rise 1 = 5.297ms, toff_delay 1 = 0ms, toff_delay 0 = 2.43ms, toff_fall 1 = 5.328ms, toff_fall 0 = 3ms, on_off_config 1 = 0x1f on_off_config 0 = 0x1e 4676 g14 v out0 200mv/div i in0 1a/div 10s/div figure 44 circuit at 12v in , no load on v out0 prior to application of short circuit 4676 g15 4676fb for more information www.linear.com/LTM4676 ltm 4676
13 read_temperature_2 (control ic temperature error) vs junction temperature, run n = 0v read_vin (input voltage readback telemetry) error vs sv in , run n = 0v mfr_read_iin n (input current readback) error vs (i vinn + i svin ), fcm, i outn swept from 0a to 13a, one channel at a time, run 1-n = 0v single phase single output short- circuit protection at full load read_vout n (output voltage readback) error vs v outn i outn = no load, run 1-n = 0v read_iout n (output current readback) error vs i outn typical p er f or m ance c harac t eris t ics t a = 25c, 12v in to 1v out , unless otherwise noted. actual temperature (c) ?45 ?1.0 measurement error (c) ?0.8 ?0.4 ?0.2 0 1.0 0.4 ?5 35 55 4676 g19 ?0.6 0.6 0.8 0.2 ?25 15 75 95 115 v out0 200mv/div i in0 1a/div 10s/div figure 44 circuit at 12v in , 77m load on v out0 prior to application of short circuit 4676 g16 v out (v) 0.5 measurement error (mv) 0 20 40 60 4.5 4676 g17 ?20 ?40 ?10 10 30 50 ?30 ?50 ?60 1.5 2.5 3.5 1.0 5.0 2.0 3.0 4.0 5.5 specified upper limit specified lower limit channel 0 channel 1 i out (a) 0 ?300 measurement error (ma) ?200 ?100 0 100 channel 0 channel 1 200 300 3.25 6.50 9.75 13.00 specified upper limit specified lower limit 4676 g18 sv in (v) 4 ?600 measurement error (mv) ?400 ?200 0 200 400 600 10 16 22 28 specified upper limit specified lower limit 4676 g20 i inn + i svin (a) 0 ?200 measurement error (ma) ?100 0 100 200 0.2 0.4 0.6 0.8 4676 g21 1.0 1.2 1.4 channel 0 channel 1 specified upper limit specified lower limit 4676fb for more information www.linear.com/LTM4676 ltm 4676
14 p in func t ions package row and column labeling m ay vary among module products. review each package layout carefully. gnd ( a4, a6-10, b4-b9, c4, c6-c9, d4, d7, e3, f3, f10, g3, g10-12, h3, h10, j4, j10, k4, k7-9, l4-9, m4, m6-10): power ground of the LTM4676. power return for v out0 and v out1 . v out0 ( a 1-3, b 1-3, c 1-3, d 1-3): channel 0 output voltage . v osns0 + ( d 9): channel 0 positive differential voltage sense input. together, v osns0 + and v osns0 C serve to kelvin- sense the v out0 output voltage at v out0 s point of load (pol) and provide the differential feedback signal directly to channel 0 s feedback loop. v out0 can regulate up to 4.0v output. command v out0 s target regulation voltage by serial bus. its initial command value at sv in power- up is dictated by nvm ( non-volatile memory) contents (factory default : 1.000 v)or, optionally, may be set by configuration resistors; see v out0cfg , v trim0cfg and the applications information section. v osns0 C (e9): channel 0 negative differential voltage sense input. see v osns0 + . typical p er f or m ance c harac t eris t ics t a = 25c, 12v in to 1v out , unless otherwise noted. read_out of 20 LTM4676s (dc1811) 12v in , 1v out , t j = C40c, i outn = 13a, system having reached thermally steady-state condition, no airflow read_out of 20 LTM4676s (dc1811) 12v in , 1v out , t j = 25c, i outn = 13a, system having reached thermally steady-state condition, no airflow read_out of 20 LTM4676s (dc1811) 12v in , 1v out , t j = 125c, i outn = 13a, system having reached thermally steady-state condition, no airflow read_iout channel readback (a) 13.12500 13.15625 13.18750 13.21875 13.25000 13.28125 13.31250 13.34375 13.37500 0 number of channels 2 4 6 8 10 12 4676 g22 read_iout channel readback (a) 13.00000 13.03125 13.06250 13.09375 13.12500 13.15625 13.18750 13.21875 13.25000 0 number of channels 2 4 6 8 10 12 4676 g23 read_iout channel readback (a) 12.96875 13.00000 13.03125 13.06250 13.09375 13.12500 13.18750 13.15625 13.21875 0 number of channels 2 4 6 8 10 12 4676 g24 v orb0 + (d10): channel 0 positive readback pin. shorted to v osns0 + internal to the LTM4676. if desired, place a test point on this node and measure its impedance to v out0 on ones hardware ( e.g., motherboard, during in circuit test ( ict) post-assembly process) to provide a means of verifying the integrity of the feedback signal connection between v osns0 + and v out0 . v orb0 C (e10): channel 0 negative readback pin. shorted to v osns0 C internal to the LTM4676. if desired, place a test point on this node and measure its impedance to gnd on ones hardware ( e.g., motherboard, during ict post-assembly process) to provide a means of verifying the integrity of the feedback signal connection between v osns0 C and gnd (v out0 power return). v out1 ( j 1-3, k 1-3, l 1-3, m 1-3): channel 1 output voltage . v osns1 ( h9): channel 1 positive voltage sense input. to - gether, v osns1 and sgnd serve to kelvin-sense the v out1 output voltage at v out1 s pol and provide the differential feedback signal directly to channel 1 s feedback loop. v out1 can regulate up to 5.4 v output. command v out1 s target regulation voltage by serial bus . its initial command value at sv in power-up is dictated by nvm (non-volatile 4676fb for more information www.linear.com/LTM4676 ltm 4676
15 p in func t ions memory) contents ( factory default: 1.000 v)or, option- ally, may be set by configuration resistors; see v out1cfg , v trim1cfg and the applications information section. sgnd ( f7-8, g7-8): channel 1 negative differential volt- age sense input. see v osns1 . additionally, sgnd is the signal ground return path of the LTM4676. if desired, one may place a test point on one of the four sgnd pins and measure its impedance to gnd on ones hardware (e.g., motherboard, during ict post-assembly process) to pro - vide a means of verifying the integrity of the feedback signal connection between the other three sgnd pins and gnd (v out1 power return). sgnd is not electrically connected to gnd internal to the LTM4676. connect sgnd to gnd at v out1 s pol negative voltage sense point. v orb1 (j9): channel 1 positive readback pin. shorted to v osns1 internal to the LTM4676. at ones option, place a test point on this node and measure its impedance to v out1 on ones hardware ( e.g., motherboard, during ict post-assembly process) to provide a means of verifying the integrity of the feedback signal connection between v out1 and v osns1 . v in0 ( a11-12, b11-12, c11-12, d11-12, e12): positive power input to channel 0 switching stage. provide suf- ficient decoupling capacitance in the form of multilayer ceramic capacitors ( mlccs) and low esr electrolytic (or equivalent) to handle reflected input current ripple from the step-down switching stage. mlccs should be placed as close to the LTM4676 as physically possible. see layout recommendations in the applications information section. v in1 ( h12, j11-12, k11-12, l11-12, m11-12): positive power input to channel 1 switching stage. provide suf- ficient decoupling capacitance in the form of mlccs and low esr electrolytic ( or equivalent) to handle reflected input current ripple from the step-down switching stage. mlccs should be placed as close to the LTM4676 as physically possible. see layout recommendations in the applications information section. sw 0 (b10): switching node of channel 0 step-down converter stage. used for test purposes or emi-snubbing heavier than that supported by snub 0 . may be routed a short distance to a local test point to monitor switching action of channel 0, if desired, but do not route near any sensitive signals; otherwise, leave electrically isolated (open). sw 1 (l10): switching node of channel 1 step-down converter stage. used for test purposes or emi-snubbing heavier than that supported by snub 1 . may be routed a short distance to a local test point to monitor switching action of channel 1, if desired, but do not route near any sensitive signals; otherwise, leave open. snub 0 ( a 5): access to channel 0 switching stage snubber capacitor. connecting an optional resistor from snub 0 to gnd can reduce radiated emi, with only a minor penalty towards power conversion efficiency. see the applications information section. pin should otherwise be left open. snub 1 ( m 5): access to channel 1 switching stage snubber capacitor. connecting an optional resistor from snub 0 to gnd can reduce radiated emi, with only a minor penalty towards power conversion efficiency. see the applications information section. pin should otherwise be left open. sv in ( f 11-12): input supply for LTM4676 s internal control ic. in most applications, sv in connects to v in0 and/or v in1 , in which case no external decoupling beyond that already allocated for v in0 /v in1 is required. if sv in is operated from an auxiliary supply separate from v in0 /v in1 , decouple this pin to gnd with a capacitor (0.1 f to 1f). intv cc ( f9, g9): internal regulator, 5 v output. when operating the LTM4676 from 5.75v sv in 26.5 v, an ldo generates intv cc from sv in to bias internal control circuits and the mosfet drivers of the LTM4676. no exter- nal decoupling is required. intv cc is regulated regardless of the run n pin state. when operating the LTM4676 with 4.5v sv in < 5.75 v, intv cc must be electrically shorted to sv in . v dd33 ( j 7): internally generated 3.3 v power supply output pin. this pin should only be used to provide ex- ternal current for the pull-up resistors required for gpio n , share_clk, and sync, and may be used to provide external current for pull-up resistors on run n , sda, scl and alert. no external decoupling is required. 4676fb for more information www.linear.com/LTM4676 ltm 4676
16 p in func t ions v dd25 ( j 6): internally generated 2.5 v power supply output pin. do not load this pin with external current; it is used strictly to bias internal logic and provides current for the internal pull-up resistors connected to the configuration- programming pins. no external decoupling is required. asel (g4): serial bus address configuration pin. on any given i 2 c/smbus serial bus segment, every device must have its own unique slave address. if this pin is left open, the LTM4676 powers up to its default slave address of 0x4f ( hexadecimal), i.e., 1001111 b ( industry standard convention is used throughout this document : 7- bit slave addressing). the lower four bits of the LTM4676s slave address can be altered from this default value by connecting a resistor from this pin to sgndhence configuring the 7-bit slave address of the LTM4676 to one of 16 supported values. minimize capacitanceespecially when the pin is left opento assure accurate detection of the pin state. f swphcfg (h4): switching frequency, channel phase- interleaving angle and phase relationship to sync configuration pin. if this pin is left open or, if the LTM4676 is configured to ignore pin-strap ( rconfig) resistors , i.e., mfr_config_all[6] = 1 b then the LTM4676s switching frequency ( frequency_ switch) and channel phase relationships ( with respect to the sync clock; mfr_pwm_config[2:0]) are dictated at sv in power- up according to the LTM4676s nvm contents. default factory values are : 500 khz operation; channel 0 at 0; and channel 1 at 180 c ( convention throughout this document: a phase angle of 0 means the channels switch node rises coincident with the falling edge of the sync pulse). connecting a resistor from this pin to sgnd ( and using the factory- default nvm setting of mfr_ config_ all[6] = 0 b ) allows a convenient way to configure multiple LTM4676s with identical nvm contents for different switching frequen - cies of operation and phase interleaving angle settings of intra- and extra-module-paralleled channelsall, without gui intervention or the need to custom pre-program module nvm contents . ( see the applications information section.) minimize capacitanceespecially when the pin is left opento assure accurate detection of the pin state. v out0cfg (g5): output voltage select pin for v out0 , coarse setting. if the v out0cfg and v trim0cfg pins are both left openor, if the LTM4676 is configured to ignore pin - strap ( rconfig) resistors, i.e ., mfr _ config_ all[6] = 1 b then the LTM4676s target v out0 output voltage setting ( vout_ command 0 ) and associated power- good and ov/ uv warning and fault thresholds are dictated at sv in power-up according to the LTM4676s nvm contents. a resistor connected from this pin to sgnd in combination with resistor pin settings on v trim0cfg , and using the factory-default nvm setting of mfr_config_all [6] = 0 b can be used to config- ure the LTM4676s channel 0 output to power-up to a vout_command value ( and associated output voltage monitoring and protection / fault - detection thresholds ) different from those of nvm contents. (see the applications information section.) connecting resistor (s ) from v out0 cfg to sgnd and/ or v trim0cfg to sgnd in this manner allows a convenient way to configure multiple LTM4676s with identical nvm contents for different output voltage settingsall without gui intervention or the need to custom-pre-program module nvm contents. minimize capacitanceespecially when the pin is left opento assure accurate detection of the pin state. note that use of rconfigs on v out0cfg /v trim0cfg can affect the v out0 range setting (mfr_pwm_config[6]) and loop gain. v trim0cfg (h5): output voltage select pin for v out0 , fine setting. works in combination with v out0cfg to affect the vout_command ( and associated output voltage monitoring and protection / fault - detection thresholds ) of channel?0, at sv in power-up . ( see v out0cfg and the applications information section.) minimize capacitance especially when the pin is left opento assure accurate detection of the pin state. note that use of rconfigs on v out0cfg /v trim0cfg can affect the v out0 range setting (mfr_pwm_config[6]) and loop gain. v out1 cfg ( g 6): output voltage select pin for v out1 , coarse setting. if the v out1cfg and v trim1cfg pins are both left open or, if the LTM4676 is configured to ignore pin - strap (rconfig) resistors, i.e., mfr_config_all [6] = 1 b then the LTM4676s target v out1 output voltage setting (vout_command 1 ) and associated power good and ov/uv warning and fault thresholds are dictated at sv in power-up according to the LTM4676s nvm contents, in precisely the same fashion that the v out0 cfg and v trim0 cfg pins affect the respective settings of v out0 / channel 0. (see v out0cfg , v trim0cfg and the applications information 4676fb for more information www.linear.com/LTM4676 ltm 4676
17 p in func t ions section.) minimize capacitanceespecially when the pin is left opento assure accurate detection of the pin state. note that use of rconfigs on v out1cfg /v trim1cfg can affect the v out1 range setting (mfr_pwm_config[5]) and loop gain. v trim1cfg (h6): output voltage select pin for v out1 , fine setting. works in combination with v out1cfg to affect the vout_command ( and associated output voltage monitoring and protection / fault - detection thresholds ) of channel?1, at sv in power-up . ( see v out1cfg and the applications information section.) minimize capacitance especially when the pin is left opento assure accurate detection of the pin state. note that use of rconfigs on v out1cfg /v trim1cfg can affect the v out1 range setting (mfr_pwm_config[5]) and loop gain. sync (e7): pwm clock synchronization input and open- drain output pin. the setting of the frequency_switch register dictates whether the LTM4676 is a sync master or sync slave module. when the LTM4676 is a sync master, frequency_switch contains the commanded switching frequency of channels 0 and 1 in pmbus linear data formatand it drives its sync pin low for 500ns at a time , at this commanded rate. whereas, a sync slave uses frequency_switch=0x0000 and does not pull its sync pin low. the LTM4676s pll synchronizes the LTM4676s pwm clock to the waveform present on the sync pinand therefore, a resistor pull-up to 3.3v is required in the application, regardless of whether the LTM4676 is a sync master or slave. exception: driving the sync pin with an external clock is permissible; see the applications information section for details. scl (e6): serial bus clock open-drain input ( can be an input and output, if clock stretching is enabled). a pull-up resistor to 3.3 v is required in the application for digital communication to the smbus master(s) that nominally drive this clock. the LTM4676 will never encounter scenarios where it would need to engage clock stretching unless scl communication speeds exceed 100khzand even then, LTM4676 will not clock stretch unless clock stretching is enabled by means of setting mfr_ config_ all[1] = 1 b . the factory- default nvm configuration setting has mfr_config_all [1] = 0 b : clock stretching disabled. if communication on the bus at clock speeds above 100 khz is required, the users smbus master(s) need to implement clock stretching support to assure solid serial bus communications, and only then should mfr_config_all[1] be set to 1 b . when clock stretching is enabled, scl becomes a bidirectional, open- drain output pin on LTM4676. sda (d6): serial bus data open-drain input and output. a pull-up resistor to 3.3v is required in the application. alert (e5): open-drain digital output. a pull-up resistor to 3.3 v is required in the application only if smbalert interrupt detection is implemented in one s smbus system. share _ clk ( h 7): share clock, bidirectional open - drain clock sharing pin. nominally 100 khz. used for synchronizing the time base between multiple LTM4676s (and any other linear technology devices with a share_ clk pin)to realize well-defined rail sequencing and rail tracking. tie the share_clk pins of all such devices together; all devices with a share_ clk pin will synchronize to the fastest clock. a pull-up resistor to 3.3 v is only re - quired when synchronizing the time base between devices. gpio 0 , gpio 1 ( e 4 and f 4, respectively): digital, programmable general purpose inputs and outputs. open-drain outputs and/or high impedance inputs. the LTM4676 s factory - default nvm configurations for mfr_ gpio_ propagate n 0x 6893and mfr_ gpio_ response n 0xc0are such that : (1) when a channel- specific fault condition is detectedsuch as channel ot ( overtemperature) or output uv/ ov the respective gpio n pin pulls logic low ; (2) when a non-channel specific fault condition is detectedsuch as input ov or control ic otboth gpio n pins pull logic low ; (3) the LTM4676 ceases switching action on channel 0 and 1 when its respective gpio n pin is logic low. most significantly, this default configuration provides for graceful integration and interoperation of LTM4676 with paralleled channel(s) of other LTM4676(s)in terms of properly coordinating efforts in starting, ceasing, and resuming switching action and output voltage regulation, in unison all without gui intervention or the need to custom-preprogram module nvm contents. pull-up resistors from gpio n to 3.3v are required for proper operation in the vast majority of applications. (only if the LTM4676 s mfr_ gpio_ response n value were set to 0 x00 might pull-ups be 4676fb for more information www.linear.com/LTM4676 ltm 4676
18 p in func t ions unnecessary. see the applications information section for details.) wp (k6): write protect pin, active high. an internal 10a current source pulls this pin to v dd33 . if wp is open circuit or logic high, only i 2 c writes to page, operation, clear_faults, mfr_clear_peaks and mfr_ee_unlock are supported. additionally, individual faults can be cleared by writing 1 b s to bits of interest in registers prefixed with status. if wp is low, i 2 c writes are unrestricted. run 0 , run 1 ( f5 and f6, respectively): enable run input for channels 0 and 1, respectively. open-drain input and output. logic high on these pins enables the respective outputs of the LTM4676. these open-drain output pins hold the pin low until the LTM4676 is out of reset and sv in is detected to exceed vin_on. a pull-up resistor to 3.3v is required in the application . do not pull run logic high with a low impedance source. tsns 0a , tsns 1a ( d5 and j5, respectively): temperature sensor excitation and measurement ports for channels 0 and 1, respectively. normally, connect these pins to tsns 0b and tsns 1b , respectively, to allow the LTM4676 to monitor its channel 0 and 1 internal thermal sensors. see the applications information section for information on how to use tsns 1a to monitor an auxiliary ( outside) temperature sensor, e.g., a pn junction on the die of a microprocessor. tsns 0b , tsns 1b ( c5 and k5, respectively): thermal sensor inputs for channels 0 and 1, respectively. see tsns 0a and tsns 1a . i sns0a + , i sns1a + ( f2 and h2, respectively): control ic current sense positive port inputsfor channels 0 and?1, respectively. connect to i sns0b + and i sns1b + , respectively. i sns0b + , i sns1b + ( f1 and h1, respectively): positive current sense signal kelvin connections for channels 0 and?1, respectively. see i sns0a + and i sns1a + . i sns0a C , i sns1a C ( e2 and g2, respectively): control ic current sense negative port inputs for channels 0 and 1, respectively. connect to i sns 0b C and i sns 1b C , respectively . i sns0b C , i sns1b C ( e1 and g1, respectively): negative current sense signal kelvin connections for channels 0 and 1, respectively. see i sns0a C /i sns1a C . comp 0a , comp 1a ( e8 and h8, respectively): current control threshold and error amplifier compensation nodes for channels 0 and 1, respectively. the trip threshold of each channels current comparator increases with a respective rise in comp n a voltage. small filter capacitors (22pf) internal to the LTM4676 on these comp pins ( ter- minated to sgnd) introduce high frequency roll off of the error-amplifier response, yielding good noise rejection in the control loop. see comp 0b /comp 1b . comp 0b , comp 1b ( d8 and j8, respectively): internal loop compensation networks for channels 0 and 1, respectively. for the vast majority of applications, the internal, default loop compensation of the LTM4676 is suitable to apply as is, and yields very satisfactory re - sults: apply the default loop compensation to the control loops of channels 0 and 1 by simply connecting comp 0a to comp 0b and comp 1a to comp 1b , respectively. whereas , when more specialized applications require a personal touch the optimization of control loop response, this can be easily accomplished by connecting ( an) r-c network (s) from comp 0a and/ or comp 1a terminated to sgnd and leaving comp 0b and/or comp 1b open, as desired. dnc ( c10, e11, h11, k10): do not connect these pins to external circuitry. solder these pins only to mounting pads on the pc board for mechanical integrity. these pads must remain electrically open cir cuit. 4676fb for more information www.linear.com/LTM4676 ltm 4676
19 s i m pli f ie d b lock diagra m decoupling r equire m en t s + + v in0 v out0 v in 5.75v to 26.5v sw 0 snub 0 gnd i sns0b ? i sns0b + i sns0a + i sns0a ? tsns0b tsns0a v osns0 + v osns0 ? local high freq mlccs x1 comp 0a comp 0b v out1 sw 1 snub 1 gnd i sns1b ? i sns1b + i sns1a + i sns1a ? tsns1b tsns1a v osns1 [+] sgnd [/v osns1 ? ] comp 1a controller signal gnd comp 1b sync asel 4676 f01 v dd25 v out0cfg v trim0cfg v trim1cfg v out1cfg f swphcfg scl 5v tolerant; pull-up resistors not shown 5v tolerant; pull-up resistors not shown 3.3v tolerant; pull-up resistor not needed sda alert wp run 0 run 1 gpio 0 gpio 1 share_clk c out0lf c out1lf c out1hf c out0hf v out0 adjustable up to 4.0v up to 13a sv in 1f 2.2nf 1f mt0 600nh 600nh thermal sensor thermal sensor mb0 mt1 mb1 2.2f 2.2f intv cc v dd33 v in1 c inh c inl thermal sensor analog readback signals to error amplifier power control analog section power management digital section + ? load0 local high freq mlccs load1 + v out1 adjustable up to 5.4v up to 13a 2.2nf internal comp spi slave spi master sync driver osc (32mhz) digital engine eeprom rom ram internal comp adc 3.3v tolerant; pull-up resistors not shown 3.3v tolerant; pull-up resistor not shown configuration resistors terminating to sgnd not shown figure 1. simplified LTM4676 block diagram symbol parameter conditions min typ max units c inh external high frequency input capacitor requirement (5.75v v in 26.5v, v outn commanded to 1.000v) i out0 = 13a, 3 22f, or 4 10f i out1 = 13a, 3 22f, or 4 10f 40 66 f c outn hf external high frequency output capacitor requirement (5.75v v in 26.5v, v outn commanded to 1.000v) i out0 = 13a i out1 = 13a 400 400 f f t a = 25c. using figure 1 configuration. 4676fb for more information www.linear.com/LTM4676 ltm 4676
20 func t ional diagra m + v in0 c inh c inl + c out0lf (computed total input current, i vino + i vin1 + i svin : read_iin) (computed channel 0 input current, i vin0 + 1/2 ? i svin : mfr_read_iin 0 ) (computed channel 1 input current, i vin1 + 1/2 ? i svin : mfr_read_iin 1 ) v in 5.75v to 26.5v (sv in telemetry: read_vin and mfr_vin_peak) (pwm 0 telemetry: read_duty_cycle 0 ) (pwm1 telemetry: read_duty_cycle 1 ) (i out0 telemetry: read_iout 0 and mfr_iout_peak 0 ) (i out1 telemetry: read_iout 1 and mfr_iout_peak 1 ) channel 0 thermal sensor (telemetry: read_temperature_1 0 and mfr_temperature_1_peak 0 ) channel 1 thermal sensor (telemetry: read_temperature_1 1 and mfr_temperature_1_peak 1 ) + + + ? ? ? sv in intv cc v dd33 v in1 int filter mt0 mt1 mb1 mb0 power control analog section v out0 gnd i sns0b ? c out0hf c out1lf c out1hf v out0 adjustable up to 4.0v up to 13a v out1 adjustable up to 5.4v up to 13a sw 0 snub 0 optional snubber resistor for moderate reduction in emi (size: eia0603 ~eia2512) r snub0 up to 2w optional snubber resistor for moderate reduction in radiated emi (size: eia0603 ~eia2512) r snub1 up to 2w z isns0b ? i sns0b + v out1 gnd i sns1b ? sw 1 snub 1 i sns1b + z isns0b + i sns0a + tsns 0b tsns 0a ?i sns0a , channel 0 current sense signal channel 1 current sense signal, ?i sns1a channel 1 (v out1 ) voltage feedback signal (differential when terminating sgnd at load 1 as shown) ?v osns0 , differential feedback signal channel 0 (v out0 ) voltage feedback signal channel 0 current demand signal channel 1 current demand signal channel 0 internal loop compensation channel 1 internal loop compensation power controller thermal sensor (telemetry: read_temperature_2) z isns0a z comp0b i sns0a ? i sns1a + tsns1b tsns1a i sns1a ? v osns0 + v osns0 ? v osns1 [+] sgnd [/v osns1 ? ] comp 0a comp 0b scl sda wp run 0 run 1 gpio 0 gpio 1 share_clk alert comp 1a comp 1b tmux 2a 30a current mode pwm ctrl. loops, lin. regulators, dacs adc, uv/ov comparators, vco and pll, mosfet drivers and power switch logic + ? ?v osns0 v osns1 ?i sns0a ?i sns1a sv in 39 pwm0 pwm1 8:1 mux v tsns dacs, ov/uv comparators, other power management digital section digital engine, including: rom, ram, nvm and oscillator 16-bit adc spi slave r r to e/a 22pf 22pf 1nf + 20k 1nf + 20k a = 1 r r local high freq mlccs local high freq mlccs (v out0 telemetry: read_vout 0 and mfr_vout_peak 0 ) (v out1 telemetry: read_vout 1 and mfr_vout_peak 1 ) (load0 power consumption telemetry: read_pout 0 ) load0 z comp1b + z isns1a (load1 power consumption telemetry: read_pout 1 ) load1 controller signal gnd (switching frequency telemetry: read_frequency) sync v dd25 asel f swphcfg v out0cfg v trim0cfg con?guration resistors terminating to sgnd not shown v out1cfg v trim1cfg 4676 fd 14.3k 6 3.3v tolerant; pull-up resistor not shown spi master digital engine, main control eeprom ram sync driver rom program v dd33 compare i 2 c-based smbus interface with pmbus command set (10khz to 400khz compatible) channel timing management uvlo osc (32mhz) config detect sinc 3 v dd33 v dd33 10a 5v tolerant; pull-up resistors not shown 5v tolerant; pull-up resistors not shown 3.3v tolerant; pull-up resistor not needed 3.3v tolerant; pull-up resistors not shown z isns1b ? z isns1b + 4676fb for more information www.linear.com/LTM4676 ltm 4676
21 tes t c ircui t s test circuit 1. LTM4676 at e high v in operating range configuration, 5.75v v in 26.5v test circuit 2. LTM4676 at e low v in operating range configuration, 4.5v v in 5.75v c inh 10f 6 c inl 150f v in 5.75v to 26.5v c outh0 100f 4 v out0 1v adjustable up to 13a v out1 1v adjustable up to 13a v in0 v in1 sv in v dd33 scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk wp v out0 tsns 0a tsns 0b i sns0a + i sns0b + i sns0a ? i sns0b ? v osns0 + v osns0 ? v out1 tsns 1a tsns 1b i sns1a + i sns1b + i sns1a ? i sns1b ? v osns1 sgnd intv cc v dd25 sw 0 sw 1 snub 0 snub 1 comp 0a comp 0b comp 1a comp 1b asel f swphcfg v out0cfg v trim0cfg v out1cfg v trim1cfg gnd + c outl0 opt* + c outl1 opt* + load c outh1 100f 4 LTM4676 load smbus interface with pmbus command set on/off control, fault management and power sequencing pwm clock synch time base synch (pull-up resistors on digital i/o pins not shown) r th1 30.1k *c outl0 , c outl1 not used in ate testing r th0 30.1k 4676 tc01 c th1 470pf c th0 470pf r th1 30.1k *c outl0 , c outl1 not used in ate testing r th0 30.1k c th1 470pf c th0 470pf c inh 10f 6 c inl 150f v in 4.5v to 5.75v c outh0 100f 4 v out0 1v adjustable up to 13a v out1 1v adjustable up to 13a v in0 v in1 sv in v dd33 scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk wp v out0 tsns 0a tsns 0b i sns0a + i sns0b + i sns0a ? i sns0b ? v osns0 + v osns0 ? v out1 tsns 1a tsns 1b i sns1a + i sns1b + i sns1a ? i sns1b ? v osns1 sgnd intv cc v dd25 sw 0 sw 1 snub 0 snub 1 comp 0a comp 0b comp 1a comp 1b asel f swphcfg v out0cfg v trim0cfg v out1cfg v trim1cfg gnd + load c outh1 100f 4 LTM4676 load smbus interface with pmbus command set on/off control, fault management and power sequencing pwm clock synch time base synch (pull-up resistors on digital i/o pins not shown) 4676 tc02 c outl0 opt* + c outl1 opt* + 4676fb for more information www.linear.com/LTM4676 ltm 4676
22 o pera t ion the ltc3880 data sheet is an essential reference docu- ment for this product. to obtain it go to: www.linear.com/ltc3880 p ower m odule i ntroduction the LTM4676 is a highly configurable dual 13 a output standalone nonisolated switching mode step- down dc/dc power supply with built-in eeprom nvm (non- volatile memory) and i 2 c-based pmbus/smbus 2-wire serial communication interface capable of 400 khz scl bus speed. tw o output voltages can be regulated (v out0 , v out1 collectively, v outn ) with a few external input and output capacitors and pull- up resistors. readback telemetry data of average input and output voltages and currents, channel pwm duty cycles, and module temperatures are continually digitized cyclically by an integrated 16- bit adc (analog-to-digital converter). many fault thresholds and responses are customizable. data can be autonomously saved to eeprom when a fault occurs, and the resulting fault log can be retrieved over i 2 c at a later time, for analysis. the LTM4676 provides precisely regulated output voltages (1%) between 0.6 vdc to 4vdc (v out0 ) and between 0.6vdc to 5.4vdc (v out1 ). the target output voltage can be set according to pin-strapping resistors (v outn cfg and/or v trimn cfg pins), nvm/register settings, and/or can be altered on the fly via the i 2 c interface. the nvm factory-default switching frequency is 500 khz and the phase- interleaving angle between its two channels is 180. channel switching frequency, phase angle, and phase relationship with the falling edge of the sync pin waveform can be configured according to a pin- strap resistor (f swphcfg pin) and nvm/register settingsthough, not on the fly during regulation. the 7- bit i 2 c slave address of the module defaults to 0 x4f, but the least significant four bits of the address can be altered by the presence of the asel resistoryielding 16 possible slave addresses. with the exception of the asel pin, the module can be configured to ignore all pin-strap resistors, if desired (see mfr_config_all[6]). the slave address cannot be changed over i 2 c. the LTM4676 control ic is a slightly modified version of the lt c ? 3880; differences between the ltc3880 and the LTM4676s control ic are outlined in table 1 of this data sheetin the applications information section. an indexed list of supported pmbus (i 2 c) and manu- facturer-specific transaction command codes, register map documentation , register-by-register factory-default settings and the corresponding communication protocols, payload size and data formats for the LTM4676s control ic are provided in the ltc3880 data sheetagain, with exceptions noted in table 1 of this data sheet. therefore, the ltc3880 data sheet is an essential reference for all LTM4676 users. major features of the LTM4676 strictly from a dc/dc converter power delivery point of view are as follows: n up to 13 a output current delivery from each of tw o integrated power stages (see front page figure)or up to 26a output, combined (see figure 35). n wide input voltage range: dc/dc step-down con- version from 5.75v to 26.5v input (see figure 44). n dc/ dc step- down conversion from 4.5 v to 5.75 v input, connecting sv in to intv cc (see figure 35). n dc/ dc step- down conversion possible from less than 4.5v input when an auxiliary 5 v bias supply powers sv in and intv cc (see figure 37). n output voltage range : 0.5 v to 4 v on v out0 , 0.5 v to 5.4v on v out1 . ( see figure 42 for dual phase single 5v output operation with reduced telemetry.) n differential remote sensing of v out0 ( v osns 0 + / v osns0 C ) and v out1 (v osns1 /sgnd). n start- up into a pre- biased load without sinking current. n four LTM4676s can be paralleled to deliver up to 100a (see figure 39). n one LTM4676 can be paralleled with three ltm4620a or ltm4630 modules to deliver up to 130 a; infer rail status and telemetry of paralleled ltm4620a or ltm4630 via the sole LTM4676 (see figure 40.) n discontinuous mode and burst mode operation available for higher light - load efficiency ( mfr _ pwm _ mode n [1:0]). 4676fb for more information www.linear.com/LTM4676 ltm 4676
23 o pera t ion n output current limit and overvoltage protection. n three integrated temperature sensors, over/under- temperature protection. n constant frequency peak current mode control. n configurable switching frequency , 250 khz to 1mhz; synchronizable to external clock; seven configurable channel phase interleaving settings. n internal loop compensation provided; external loop compensation can be applied, if preferred. n integrated snubber capacitors enable emi reduction by placing external snubber resistors adjacent to the module (see figures 32 and 33). n low profile (16mm 16mm 5.01 mm) bga package power solution requires only input and output capaci- tors; at most, nine pull-up resistors for open-drain digital signals; at most, six pull-down resistors to configure all possible pin-strapping options. features of the LTM4676 that enable power system management, rail sequencing, and fault monitoring and reporting are as follows: n i 2 c- based pmbus/ smbus 2-wire serial communication interface ( sda, scl) with alert interrupt pin, scl clock capable of 400 khz bus communication speeds with clock low extendingor 100khz, otherwise. n configurable output v oltage. n configurable input undervoltage comparators (uvlo rising, uvlo falling). n configurable switching frequency. n configurable current limit. n configurable output over/undervoltage comparators. n configurable t urn-on and turn-off delay times. n configurable output ramp rise and fall t imes. n non-volatile configuration memory ( nvm eeprom) to configure aforementioned settings, and moreyield- ing standalone operation, if desired, and also enabling in-situ changes to the LTM4676s configuration in embedded designs. n monitoring and reporting of telemetry data: average output and input currents and voltages, internal tem - peratures, and power stage duty cycles continuously digitized cyclically by a 16-bit adc. ? peak observed output current and voltage, input voltage, and module temperatures can be polled and cleared/reset. ? adc latency not greater than 100ms, nominal. ? option to monitor one external temperature in lieu of channel 1 (v out1 ) module power stage temperature . n monitoring, reporting, and configurable response to latching and non-latching individual fault and/or warning status, including but not limited to: ? output over/under voltages. ? input (sv in ) over/undervoltages. ? module input and power stage output overcurrents. ? module power stage over/undertemperatures. ? internal control ic overtemperature. ? communication, memor y and logic (cml) faults. n fault logging upon detection of a fault condition. the LTM4676 can be configured to automatically upload a fault log to its nvm, consisting of: an uptime counter, peak observed telemetry, telemetry gathered from the six most recent rounds of cyclical adc data leading up to the detection of the fault that triggered fault log writing, and fault status associated with that adc history. n tw o configurable open-drain general purpose input/ output pins (gpio 0 , gpio 1 ), which can be used for: ? fault reporting, e.g., as a system interrupt signal. ? coordinating turn-on/off of the LTM4676 in multi - phase/multirail systems. ? propagating an unfiltered power good signal ( output of a v outn undervoltage comparator) to command turn-on/off of a downstream rail. 4676fb for more information www.linear.com/LTM4676 ltm 4676
24 o pera t ion n a write protect ( wp) pin and configurable write_ protect register to protect the internal configuration of ram and nvm against unintended changes via i 2 c. n time-base interconnect (share_clk, 100 khz heart- beat) for synchronization in the time domain between multiple LTM4676s. n optional external configuration resistors ( rconfigs) for setting start-up output voltages, switching fre- quency and channel-to-channel phase interleaving angle. n 16 supported slave addresses (0 x4f default), con- figured by resistor pin strapping the asel pin. p ower m odule c onfigurabilit y and r eadback d ata this section of the data sheet describes in detail all the configurable features and readable data of the LTM4676 accessible via i 2 c. the relevant register name(s) are indicated by use of all capital letters, e.g ., vin_on. refer to the ltc3880 data sheet and table 1 of this data sheet in order to identify the associated command code, payload size, data format and factory- default value for each register name of interest. specific register bits of some registers are indicated with the use of brackets, i.e ., [ and ]. the least significant bit ( lsb) of a register is bit number zero, indicated by [0]. the most significant bit of a byte -long (8-bit - long) register is bit number seven, indicated by [7]. the most significant bit ( msb) of a word- long (16-bit- long) register is bit number fifteen, indicated by [15]. multiple bits of a register can be alluded to with the use of a colon, e.g., bits 2, 1 and 0 of the mfr_pwm_config register are indicated by mfr_pwm_config[2:0]. bits can take on values of 0 b or 1 b . the subscripted b suffix indicates the numbers value is in binary. values in hexadecimal are indicated with a 0 x prefix. for example, decimal value 89 is indicated by 0 x59 and 01011001 b (8-bit-long values), as well as 0 x0059 and 0000000001011001 b (16-bit-long values). one further shorthand notion the reader will notice is the italicized n or n. n can take on a value of 0 or 1and provides an easy way to refer to registers which are paged commands, i.e., register names which have the same command code value but can be configured independently ( or yield channel-specific telemetry) for channel 0 (page 0, or 0 x 00) vs channel 1 (page 1, or 0 x 01). registers lacking an n are therefore easily identified as being global in nature, i.e., common to both channels/ outputs . for example, the switching frequency setting c ommanded by register frequency _ switch is common to both channels, and lacks n . another example: the read_vin register contains the digitized input voltage as seen at the sv in pin, and sv in is unique, i.e., common to both channels. whereas, the nominal commanded output voltage is indicated by the register vout_command n . the n indicates that vout_command can be set dif- ferently for channel 0 vs channel 1. executing the page command ( command code 0 x00) with payload 0 x00 sets the LTM4676 to write/read data pertaining to channel 0 in all subsequent i 2 c transactions until the page is changed. executing the page command with payload 0 x01 sets the LTM4676 to write/read data pertaining to channel 1 in all subsequent i 2 c transactions until the page is changed. executing the page command with payload 0 xff sets the LTM4676 to write data pertaining to channels 0 and ?1 in all subsequent i 2 c write transactions until the page is changed. reads from and writes to global registers do not require setting the page to 0 xff. reads from channel- specific ( i.e., non-global) registers when the page is set to 0xff result in the LTM4676 reporting the value on page 0x00 (i.e., channel 0-specific data). the list below itemizes aspects of the LTM4676 relating to power supply functions that are configurable by i 2 c communicationsprovided the state of the wp (write protect) pin and the write_ protect register value permit the i 2 c writesand by eeprom settings: 4676fb for more information www.linear.com/LTM4676 ltm 4676
25 o pera t ion n output start - up voltages ( vout_ command n ), the maximum commandable output voltages ( vout_ max n ), output voltage power good on ( vout_ pgood_ on n ) and off (power_ good_ off n ) thresholds, output margin high ( vout_ margin_ high n ) and margin low ( vout_ margin_ low n ) command voltages, and output over/ undervoltage warning and fault thresholds ( vout_ ov_ warn_ limit n , vout _ ov_ fault_ limit n , vout _ uv_ warn_ limit n , and vout_ uv_ fault_ limit n ). additionally , these values can be configured at sv in power- up according to resistor- pin strapping of the v out0 cfg , v trim0 cfg , v out1 cfg and/ or v trim1 cfg pins, provided mfr_ config _ all [6] = 0 b . n output voltages, on the fly, including transition rate (?v/?t), vout_transition_rate n either by i 2 c writes to the vout_command n , vout_margin_ high n , or vout_ margin_ low n registers, and / or to the operation n register. n input undervoltage - lockout, rising ( vin_ on) and input undervoltage lockout, falling ( vin_off), based on the sv in pin voltage. n switching frequency ( frequency_ switch) and channel phase- interleaving angle ( mfr_ pwm_ config[2:0]). however, these parameters can be changed via i 2 c communications only when the LTM4676 s channels are off , i .e ., not switching. additionally, these parameters can be configured at sv in power-up according to resistor-pin strapping of the f swphcfg pin, provided mfr_config_all [6] = 0 b . n output voltage turn on and turn off sequencing and associated w atchdog timers, namely: ? output voltage turn-on delay time ( the time delay from the LTM4676 being commanded to turn on, e.g., by the run n pin toggling from logic low to high, before switching action commences . ton_delay n ). ? output voltage soft-start ramp-up time (ton_ rise n ). ? the amount of time (ton_max_fault_limit n ) permitted to elapse after the LTM4676 is commanded to turn on, e.g ., by the run n pin toggling from logic low to high, after which, if the output voltage fails to exceed the output undervoltage fault threshold (vout_uv_fault_limit n ), the LTM4676s output (v outn ) is declared to have not come up in a timely manner. ? the LTM4676 s response to any such afore - mentioned ton_ max_ fault_ limit n event (ton_max_fault_response n ). ? output v oltage soft- stop ramp- down time (toff_fall n ). ? output voltage turn- off delay time ( the time delay from the LTM4676 being commanded to turn off, e.g ., by the run n pin toggling from logic high to low, before switching action ceases. toff _ delay n ). ? when commanded to turn off it outputor, when turning off its output in response to a fault configuring whether the LTM4676's output (v outn ) becomes high impedance ( high -z or three stateturning off both mt n and mbn in the power stage). (immediate off, on _ off_ config n [0] = 1 b vs configuring the output voltage to be ramped down according to toff_fall n and/or toff_delay n settings, on_off_config n [0] = 0 b ). ? the amount of time ( toff_max_warn_limit n ) permitted to elapse after the LTM4676 is supposed to have turned off its output, i.e., at the end of the period dictated by toff_fall n , after which, if the output voltage has not fallen below 12.5% of the former target voltage of regulation, the LTM4676s output (v outn ) is declared to have not powered down in a timely manner. 4676fb for more information www.linear.com/LTM4676 ltm 4676
26 o pera t ion n configurable output voltage restart time. subse - quent to the run n pin being pulled low, the LTM4676 pulls run n logic low, itself, and the output cannot be restarted until a minimum time has elapsed the restart delay time. this delay assures proper sequencing of all system rails. the minimum restart delay processed by the LTM4676 is the longer of ( toff_ delay n + toff_fall n + 136 ms) vs the commanded mfr_restart_delay n register value. at the end of this delay, the LTM4676 releases its run n pin. n configurable fault-hiccup retry delay time. when a fault occurs in which the LTM4676s fault response behavior to that fault is to reattempt power- up of its output voltage after said fault ceases to be present (e.g., infinite retry), the delay time for the LTM4676 to re-engage switching action is the longer of the mfr_retry_delay n time vs the time required for the output to decay below 12.5% of the formerly commanded output voltage value (unless this lattermost criteria, i.e., requiring the output to decay below 12.5% is negated by the setting of mfr_ chan_config n [0] to 1 b which is the LTM4676s factory-nvm default setting). n output over / undervoltage fault responses ( vout_ ov_ fault_ response n , vout _ uv_ fault_ response n ). n time- averaged current limit warning and instantaneous peak ( cycle - by - cycle) fault thresholds, and fault response ( iout_ oc_ warn_ limit n , iout _ oc_ fault_limit n , iout_oc_fault_response n ). n channel ( v out0 , v out1 ) overtemperature warning and fault thresholds, and fault response (ot_warn_ limit n , ot _ fault_ limit n , ot _ fault_ response n ). n channel ( v out 0 , v out 1 ) undertemperature fault thresholds and fault response (ut_fault_limit n , ut_fault_response n ). n input overvoltage fault threshold and response ( vin_ ov_ fault_ limit, vin _ ov_ fault_ response), based on the sv in pin voltage. n input undervoltage warning threshold ( vin_ uv_ warn_limit) based on the sv in pin voltage. n module i nput overcurrent warning threshold (iin_oc_warn_limit) the control ic within the LTM4676 module ceases switching action if control ic temperature exceeds 160c (note 12). the control ic resumes operation after a 10c cool-down hysteresis. note that these typical parameters are based on measurements in a lab oven and are not production tested. this overtemperature protection is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operat - ing junction temperature may impair device reliability or permanently damage the device. t ime -a veraged and p eak r eadback d ata time-averaged telemetry readback data accessible via i 2 c communications follow: n channel output current ( read_ iout n ) and peak observed value of read_iout n ( mfr_iout_peak n ). n channel o utput voltage ( read _ vout n ) and peak observed value of read_ vout n ( mfr_ vout_ peak n ). n channel output power (read_pout n ). n channel input current (mfr_read_iin n ) and module input current (read_iin). n channel temperatures ( read_ temperature_1 n ) and peak observed values of read_temperature_1 n (mfr_temperature_1_peak n ). n control ic temperature ( read_ temperature_2) and peak observed value ( mfr_ temperature_2_peak). n input voltage ( read_vin), based on the voltage of the sv in pin, and peak observed value of read_vin (mfr_vin_peak). n channel topside power mosfet (mtn ) duty cycle (read_duty_cycle n ) peak observed values of telemetry readback data can be cleared with the mfr_clear_peaks i 2 c command, provided the write_protect register value permits it. ( executing mfr _ clear _ peaks can be performed regard - less of the state of the wp pin.) 4676fb for more information www.linear.com/LTM4676 ltm 4676
27 o pera t ion details on the LTM4676s fault log feature follow: n fault logging is enabled when mfr_ config_ all[7] = 1 b . n a fault log is present in nvm when status_mfr_ specific n [3]reports 1 b , which is propagated to the mfr bit (bit 12) of the status_word register. n retrieving fault log data, if present, is performed with the mfr_fault_log command . 147 bytes of data are retrieved using the pmbus-defined variant to the smbus block read protocol. n the fault log contents in nvm, if present, are cleared b y executing the mfr _ fault _ log _ clear command . n the fault log will not be written if a fault log is already present in nvm. n the LTM4676 can be forced to write a fault log to its nvm by executing the mfr_fault_log_store command; the LTM4676 will behave as if a channel faulted off. note the command is nacked and a cml fault is reported if a fault log is already present at the time of executing mfr_fault_log_store. when an external stimulus pulls the LTM4676 s gpio n pin (s ) logic low, the respective channel ( v out n ) ei - ther: takes no action on it, i.e ., ignores it completely if mfr _ gpio _ response n = 0x 00; or, turns off immediately, i.e ., the power stage (s ) become high impedance ( inhibited) if mfr_ gpio_ response n = 0xc0. the mfr_gpio_propagate n register contents config- ure which fault(s) cause the LTM4676 to pull its gpio n pin(s) logic low. i 2 c communications are originated by the user s ( system s) i 2 c master device. writes/reads to/from channel 0 of the LTM4676 (v out0 : page 0 x00), to/from channel 1 of the LTM4676 (v out1 : page 0 x01), or writes to both channels 0 and 1 of the LTM4676 (v out0 and v out1 : page 0xff) are possible. the target channel(s) of interest are selected by the i 2 c master by executing the page command and sending the appropriate argument (0x00, 0x01, 0 xff) in the payload. the page command is unrestricted, i.e., not affected by the wp pin or write_protect register settings. the LTM4676 always responds to its global slave ad- dresses, 0 x5a and 0 x5b. commands sent to the global address 0 x5a act the same as if the page command were set to 0 xff, i.e., received commands are written to both channels simultaneously. commands sent to the global address 0 x5b are applied to the page active at the time of the global address transaction, i.e ., allows channel- specific command of all LTM4676 devices on the bus. i 2 c commands not listed above that relate to fault status and eeprom nvm operations follow. writing of the following is possible provided the state of the wp (write protect) pin and the write_protect register value permits the i2c writes: n soliciting ( reading) module fault status and clearing ( writing) module fault status ( clear_ faults, status _ byte n , status _ word n , status _ vout n , status_iout n , status_input, status_ temperature n , status _ cml [ communications, memory, and/or logic], and status_mfr_specific n [miscellaneous]). n storing the LTM4676s user-writable ram register data to the eeprom nvm (store_user_all). n downloading eeprom nvm data to ram registers (restore_user_all). n an a lternate means to the store _ user _ all command to directly erase and write the LTM4676s eeprom contents, protected by unlock keys, to facilitate programming of the LTM4676 eeprom in environments such as ict ( in-circuit test) and bulk programming by, e.g., embedded hardware or by the ltpowerplay gui. also, a means to directly read the LTM4676 eeprom contents (mfr_ee_unlock, mfr_ee_erase, mfr_ee_ data ). n instigating a reset of the LTM4676 without power- cycling sv in power (mfr_reset). 4676fb for more information www.linear.com/LTM4676 ltm 4676
28 o pera t ion other data that can be obtained from the LTM4676 via i 2 c communications are as follows: n soliciting the LTM4676 for its pmbus capabilities, as defined by pmbus (cap ability): ? pec ( packet error checking). note, the LTM4676 requires valid pec in i 2 c communications when mfr_ config_ all[2] = 1 b . the nvm factory- default configuration is mfr_ config_ all[2] = 0 b , i.e ., pec not required. ? i 2 c communications can be supported at up to 400khz scl bus speed. note, clock low extending (clock stretching) must be enabled on the LTM4676 to ensure robust communications above 100khz scl bus speeds, i.e ., mfr _ config_ all[1] = 1 b . the nvm factory- default configuration is mfr_ config_ all[1] = 0 b , i.e. clock stretching is disabled. ? the LTM4676 has an smbalert ( alert ) pin and does support the smbus ara ( alert response ad - dress) protocol. n soliciting the module for the maximum output voltage it can be commanded to produce ( mfr_ vout_ max n ). n soliciting the device for the data format of its output voltage-related registers (vout_mode n ). n soliciting the device for the revisions of pmbus specifica - tions that it supports ( part i : rev . 1.1; part ii: rev 1.1). n soliciting the device for the identification of the manufacturer of the LTM4676 , ltc ( mfr_id) and the manufacturer code representing the LTM4676 and revision, 0x440x (mfr_special_id). n soliciting the device for its part number , LTM4676 (mfr_model). n soliciting the module for its serial number (mfr_serial). n the digital status of the LTM4676s i/o pads and validity of the adc ( mfr_pads) and wp pin status (mfr_common[0]). the following list indicates other aspects of the LTM4676 relating to power system management and power se - quencing that are configurable by i 2 c communications provided the state of the wp ( write protect) pin and the write_ protect register value permit the i 2 cwrites and by eeprom settings: n providing multiple means to read/write data directly to a particular channel of the LTM4676 by assigning additional slave address for channels 0 and 1 (mfr_ channel_address n , mfr_rail_address n ), the benefit of which is that it reduces page command usage and associated i 2 c traffic. it also facilitates altering the same register of multiple LTM4676 in unison without invoking the pmbus group command protocol. n configuring the output voltage to be on or off by me ans other than the run n pin ( on _ off _ config n [3], operation commands) n configuring whether the LTM4676 masks pll (phase- locked loop) out - of- lock faults. (mfr_ config_ all[3]). n configuring whe ther the LTM4676 performs a clear_faults command upon itself when either run n pin toggles from logic low to logic high. (mfr_config_all[0]). n configuring whether the LTM4676 pulls run n logic low when the LTM4676 is commanded off by other means (mfr_chan_config n [4]). n configuring t he response of the LTM4676 when it is commanded to turn on its output prior to the completion of processing toff_ delay n and toff_fall n power-down sequencing (mfr_chan_ config n [3]). n configuring whether the LTM4676 s output is disabled when share_clk is held low ( mfr_chan_ config n [2]). n configuring whether the alert pin is pulled low when gpio n is pulled low by external stimulus (mfr_chan_config n [1]). 4676fb for more information www.linear.com/LTM4676 ltm 4676
29 o pera t ion n setting the value of the mfr_iin_offset n registers, representing an estimate of the current drawn by the sv in pin. the sv in pin current is not measured by the LTM4676 but the mfr_iin_offset n is used in computing and reporting channel and total module input currents (mfr_read_iin n , read_iin). n three words ( six bytes) of the LTM4676 s eeprom that are available for storing user data . ( user_data_03 n , user_data_04). n invoking or releasing several levels of i 2 c write protection (write_protect). n determining whether the user-editable ram register values are identical to the contents of the user nvm (mfr_compare_user_all). n setting the programmable output voltage range of v out to a narrower range (0.5 v to 2.75 v) in order to achieve a higher resolution of v out adjustment than is available by default ( mfr_ pwm_ config[6:5]). mfr_pwm_config cannot be changed on the fly; switching action must be off. note that altering the v out range alters the gain of the control loop and may therefore require loop compensation to be adjusted. n altering the temperature coefficient of the LTM4676s current sensing elements, if needed ( mfr _ iout _ cal_ gain_tc n ) ( uncommon to alter this parameter from its nvm-factory default setting). n altering the gain or offset of the power stage sensors ( mfr _ temp_1_gain n and mfr_ temp_1_offset n ) or that of the external temperature sensor, when an external temperature sensor is used on the tsns 1a pin. ( uncommon to alter this parameter from its nvm- factory default setting). n configuring whether the LTM4676 pulls share_clk logic low when sv in has fallen outside its uvlo thresholds ( mfr_ pwm_ config[4]). mfr _ pwm_ config cannot be changed on the fly; switching action must be off ( uncommon to alter this parameter from its nvm-factory default setting). n configuring whether the LTM4676s output voltage digital servos are active vs disengaged (mfr_pwm_ mode n [6]. uncommon to alter this parameter from its nvm-factory default settings). n configuring whether the LTM4676s current limit range is set to high range vs low range. (mfr_ pwm_ mode n [7]. not recommended to alter this parameter from its nvm-factory default settings). remaining LTM4676 status that can be queried over i 2 c communications follow: n access to three hand- shaking status bits ( mfr _ common[6:4]) to ease implementation of pmbus busy protocols, i.e., enabling fast and robust system level communication through polling of these bits to infer LTM4676 s readiness to act on subsequent i 2 c writes. ( see pmbus communication and command processing, in the applications information section.) n providing a means to determine whether the LTM4676 nvm download to ram has occurred (nvm initialized, mfr_common[3]). n providing a means other than ara protocol to de- termine whether the LTM4676 is pulling alert low (mfr_common[7]). n detecting a share_ clk timeout event (mfr_common[1]). n verifying the slave address of the LTM4676 (mfr_address). p ower m odule o ver view a dedicated remote - sense amplifier precisely kelvin- senses v out0 s load via the differential pin-pair formed by v osns0 + and v osns0 C . v out0 can be commanded to between 0.5 vdc and 4.0 vdc. v out1 is precision kelvin sensed via the differential pin-pair formed by v osns1 and signal ground of the modules internal control ic, sgnd. v out1 can be commanded to between 0.5vdc and 5.4vdc. output voltage readback telemetry is available over i 2 c (read_vout n registers). peak output voltage readback 4676fb for more information www.linear.com/LTM4676 ltm 4676
30 o pera t ion telemetry is accessible in the mfr_read_vout_peak n registers. if v osns0 C exceeds v osns + , no phase reversal of the differentially-sensed output voltage feedback signal occurs ( note 12). similarly, no phase reversal occurs when sgnd exceeds v osns1 (note 12). the typical application schematic is shown in figure 44 on the back page of this data sheet. the LTM4676 can operate from input voltages between 5.75v and 26.5 v ( see front page figure). in this con- figuration, intv cc mosfet driver and control ic bias is generated internally by an ldo fed from sv in to produce 5v at up to 100 ma peak output current. additional in- ternal ldos 3.3v (v dd33 ), derived from intv cc , and 2.5v (v dd25 ), derived from v dd33 bias the LTM4676s digital circuitry. when intv cc is connected to sv in , the LTM4676 can operate from input voltages between 4.5v and 5.75v ( see figure 35). control ic bias (sv in ) is routed independent of the inputs to the power stages (v in0 , v in1 ); this enables step-down dc/dc conversion from less than 4.5 v input ( see figure 37), so long as auxiliary power (4.5v ~ 26.5 v) is available to bias the control ic appropriately. furthermore , the inputs of the two power stages are not connected together internal to the module; therefore, dc/ dc step - down conversion from two different source power supplies can be performed. per note 6 of the electrical characteristics section, the output current may require derating for some operating scenarios. detailed derating guidance is provided in the applications information section. the LTM4676 contains dual integrated constant frequency current mode control buck regulators (channel 0 and channel 1) whose built-in power mosfets are capable of fast switching speed. the factory nvm-default switching frequency clocks sync at 500 khz, to which the regula - tors synchronize their switching frequency. the default phase-interleaving angle between the channels is 180. a pin-strapping resistor on f swphcfg configures the fre- quency of the sync clock ( switching frequency) and the channel phase relationship of the channels to each other and with respect to the falling edge of the sync signal. (not all possible combinations of switching frequency and phase-angle assignments are settable by resistor pin programming; see table 4. configure the LTM4676s nvm to implement settings not available by resistor-pin strapping.) when a f swphcfg pin-strap resistor sets the channel phase relationship of the LTM4676s channels , the sync clock is not driven by the module; instead, sync becomes strictly a high impedance input and channel switching frequency is then synchronized to sync provided by an externally-generated clock or sibling LTM4676 with pull-up resistor to v dd33 . switching frequency and phase relationship can be altered via the i 2 c interface, but only when switching action is off, i.e., when the module is not regulating either output. see the applications information section for details. internal feedback loop compensation for regulator 0 is available by connecting comp 0a to comp 0b . ( for regula- tor?1, the connection is from comp 1a to comp 1b .) with current mode control and internal feedback loop com- pensation, the LTM4676 module has sufficient stability margins and good transient performance with a wide range of output capacitorseven all-ceramic mlccs. table?20 provides guidance on input and output capacitors recommended for many common operating conditions. the linear technology module power design tool is available for transient and stability analysis. furthermore, expert users who prefer to not make use of the modules internal feedback loop compensationbut instead, tailor the feedback loop compensation specifically for his/her applicationmay do so by not connecting comp n a to comp n b : the personalized loop compensation network can be applied externally, i.e., from comp n a to sgnd, and leaving comp n b open circuit. the LTM4676 has two general purpose input/output pins, named gpio 0 and gpio 1 . the behavior of these pins is configurable via registers mfr_ gpio_ propagate n and mfr_gpio_response n . the gpio n pins are high impedance during nvm-download-to-ram initialization. these pins are intended to perform one of two primary functions, or a hybrid of the two: behave as open- drain, active low fault/warning indicators; and/or, behave as auxiliary run pins for their respective v out s. in the former case, the pins can be configured as interrupt pins, pulling active low when output under/overvoltage, input under/ overvoltage, input/output overcurrent, overtemperature, and/or communication, memory or logic ( cml) fault or warning events are detected by the LTM4676. factory 4676fb for more information www.linear.com/LTM4676 ltm 4676
31 o pera t ion nvm-default settings configure the LTM4676 for the latter case, enabling the gpio n to be bussed to paralleled siblings ( paralleled LTM4676 channels and/or modules), for purposes of coordinating orderly power- up and power- down, i.e., in unison. the LTM4676 dc/dc regulator does not feature a traditional power good ( pgood) indicator pin to indicate when the output voltage is within a few percent of the target regulation point. however, the gpio n pin can be configured as a pgood indicator. if used for event- based sequencing of downstream rails, configure gpio n as the unfiltered output of the vout_uv_fault_limit n comparator, setting bit 12 of mfr _ gpio _ propagate n to 1 b ; do not set bits 9 and 10 of mfr_gpio_propagate n for this purpose, since the propagation of power good in those latter instances is subject to the adcs latency of up to 100 ms, nominal. if it is necessary to have the desired pgood polarity appear on the gpio n pin immediately upon sv in power-upgiven that the pin will initially be high impedance, until nvm contents have downloaded to rama pull-down schottky diode is needed between the run n pin of the LTM4676 and the respective gpio n pin. ( see figure 2.) if the gpio n pin is configured as a pgood indicator, the mfr_gpio_response n must be set to ignore (0 x00), or else the LTM4676 cannot start up due to the latch-off conditions imposed. the run n pin is a bidirectional open-drain pin. this means it should never be driven logic high from a low impedance source. instead, simply provide a 10 k pull- up resistor from the run n pins to v dd33 . the LTM4676 pulls its run n pin logic low during nvm-download-to-ram initialization, when sv in is below the commanded undervoltage lockout voltage ( vin_ on, rising and vin_ off, falling), and subsequent to external stimulus pulling run lowfor a minimum time dictated by mfr_restart_delay n . bussing the respective run n and gpio n pins to sibling LTM4676 modules enables coordinated power- up/ power- down to be well orchestrated, i.e., performing turn-on and turn-off in a unified fashion. when run n exceeds 2 v, the LTM4676 initially idles for a time dictated by the ton_delay n register. after the ton_delay n time expires, the module begins ramping up the respective control loop s internal reference, starting from 0 v. in the absence of a pre-biased v outn condition, the output voltage is ramped linearly from 0v to the commanded target voltage, with a ramp-up time dictated by the ton_rise n register. in the presence of a pre-biased v outn condition, the output voltage is brought into regulation in the same manner as aforementioned, with the exception that inductor current is prevented from going negative ( the modules controller operated in discontinuous mode operation during start-up). in both cases, the output voltage reaches regulation in a consistent time, as measured with respect to run n toggling high. see start- up oscilloscope shots in the typical performance characteristics section. pulling the run n pin below 1.4 v turns off the dc/dc converter, i.e ., forces the respective regulator into a shutdown state. factory nvm-default settings configure the LTM4676 to turn off its power stage mosfets im- mediately, thereby becoming high impedance. the out- put voltage then decays according to whatever output capacitance and load impedance is present. alternatively, nvm/register settings can configure the LTM4676 to actively discharge v outn when run n is pulled logic low, according to prescribed toff_delay n delay and toff_ fall n ramp- down times. see the applications infor - mation section for details. the LTM4676 does not feature an explicit, analog track pin. rail-to-rail tracking and sequencing is handled digitally, as explained previously. LTM4676 voltage based sequencing by cascading gpio n pins into run n pins (mfr_gpio_propagate = xxx1x00xx00xxxxx b and mfr_gpio_response = 0x00) gpio 0 = v out0_uvuf gpio 1 = v out1_uvuf run 1 note: resistor or rc pull-ups on run n and gpio n pins not shown *optional signal schottky diode. only needed when accurate pgood (power good) indication is requred by the system/user immediately at sv in power up run 0 start LTM4676 4676 f02 run 0 gpio 0 = v out0_uvuf gpio 1 = v out1_uvuf to next channel in the sequence run 1 * * * * figure 2. event (voltage) based sequencing 4676fb for more information www.linear.com/LTM4676 ltm 4676
32 o pera t ion bussing the open-drain share_clk pins of all LTM4676s (and providing a pull-up resistor to v dd33 ) provides a means for all LTM4676s in the system to synchronize their time-base (or heartbeat) to the fastest share_clk clock. sharing the heartbeat amongst all LTM4676 ensures that all rails are sequenced according to expectations; it negates timing errors that could otherwise materialize due to share_clk ( time-base) tolerance and part-to- part variation. electrically connect adjacent pins i sns 0a + to i sns 0b + ; i sns 0a C to i sns0b C ; i sns1a + to i sns1b + ; and i sns1a C to i sns01b C . current sense information is derived from across the power inductors ( i sns n b + /i sns n b C pin - pairs) internal to the LTM4676 and made available to the internal control ics current control loops and adc sensors ( i snsn a + /i snsn a C ) by the aforementioned connections. output current readback telemetry is available over i 2 c (read_iout n registers). peak output current readback telemetry is available in the mfr_read_iout_peak n registers. output power readback is computed by the LTM4676 according to: read_pout n = read_vout n ? read_iout n alternating excitation currents of 2 a and 30 a are sourced from each of the tsns 0a and tsns 1a pins. connecting tsns 0a to tsns 0b , and then tsns 1a to tsns 1b , temperature sensing of the channel 0 and channel 1 power stages is realized by the LTM4676 digitizing the voltages that appear at the pnp transistor temperature sensors that reside at pins tsns 0b and tsns 1b , respectively. the LTM4676 performs what is known in the industry as delta vbe (? vbe) computations and makes channel (power stage) temperature telemetry available over i 2 c (read_temperature_1 n ). the junction temperature of the control ic within the LTM4676 is also available over i 2 c ( read_ temperature_2). observed peak channel temperatures can be read back in registers read_mfr_temperature_1_peak n . observed peak temperature of the control ic can be read back in register mfr_read_temperature_2_peak. for a fixed load current, the amplitude of the current sense information changes over temperature due to the temperature coefficient of copper ( inductor dcr), which is approximately 3900 ppm/c. this would introduce signifi - cant current readback error over the operating range of the module if not for the fact that the LTM4676s temperature readback information is used in conjunction with the per- ceived current sense signal to yield temperature-corrected current readback data. if desired, it is possible to use only the temperature readback information derived from the tsns 0a /tsns 0b pins to yield temperature-corrected current readback data for both channels 0 and 1. this frees up the channel 1 temperature sensor to monitor a temperature sensor external to the LTM4676. this is achieved by setting mfr_pwm_mode_LTM4676 0 [3] = 1 ( the nvm-factory default value is 0). this degrades the current readback accuracy of channel 1 more so when channel 0 and channel 1 are not paralleled outputs. however, the tsns 1a pin becomes available to be connected to an external diode- connected small-signal pnp transistor ( such as 2n3906) and 10 nf x7r capacitor, i.e., an external temperature sensor, whose temperature readback data and peak value is available over i 2 c (read_temperature_1 1 , mfr_read_temperature_1_peak 1 ). details on how to connect an external temperature sensor and 10 nf capacitor to the tsns 1a pin are detailed in the ltc3880 data sheet ( the tsns 1a pin of the LTM4676 is the tsns 1 pin of LTM4676s internal control ic). power stage duty cycle readback telemetry is available over i 2 c (read_duty_cycle n registers). computed channel input current readback is computed by the LTM4676 as: mfr_read_iin n = read_duty_cycle n ? read_iout n + mfr_iin_offset n computed module input current readback is computed by the LTM4676 as: read_iin = mfr _read_iin 0 + mfr _read_iin 1 where mfr_iin_offset n is a register value representing the sv in input bias current. the sv in current is not dig- itized by the module. the factory nvm-default value of mfr _ i in _ o ffset n is 30.5 ma, representing the contribution of current drawn by each of the modules 4676fb for more information www.linear.com/LTM4676 ltm 4676
33 o pera t ion channels on the sv in pin, when the power stages are operating in forced continuous mode at the factory- default switching frequency of 500 khz. see table 8 in the applications information section for recommended mfr_iin_offset n setting vs switching frequency. the aforementioned method by which input current is calculated yields an accurate current readback value even at light load currents, but only as long as the module is configured for forced continuous operation ( nvm-factory default). sv in and peak sv in readback telemetry is accessible via i 2 c in the read_ vin and mfr_ vin_ peak registers, respectively . the power stage switch nodes are brought out on the sw n pin for functional operation monitoring and for optional installation of a resistor-capacitor snubber circuit (termi - nated to gnd) for reduced emi. internal 2.2 nf snubber capacitors connected directly to the switch nodes further facilitate implementation of a snubber network, if desired. see the application information section for details. the LTM4676 features a write protect ( wp) pin. if wp is open circuit or logic high, i 2 c writes are severely restricted: only i 2 c writes to the page, operation, clear _ faults, mfr_clear_peaks, and mfr_ee_unlock commands are supported , with the exception that individual fault bits can be cleared by writing a 1 b to the respective bits in the status_* registers. register reads are never restricted. not to be confused with the wp pin, the LTM4676 features a write_protect register, which is also used to restrict i 2 c writes to register contents. refer to the ltc3880 data sheet for details. the wp pin and the write_protect register provide a level of protection against accidental changes to ram and eeprom contents. the LTM4676 supports up to 16 possible slave addresses. the factory nvm-default slave address is 0 x4f. the lower four bits of the LTM4676s slave address can be altered from this default value by connecting a resistor from this pin to sgnd. see table 5 in the applications information section for details. up to four LTM4676 modules (8 channels) can be par- alleled, suitable for powering ~100 a loads such as cpus and gpus . ( see figure 39.) the LTM4676 can be paral - leled with ltm4620a or ltm4630 modules, as well (see figures 40 and 41). eeprom the LTM4676s control ic contains an internal eeprom ( non- volatile memory, nvm) to store configuration settings and fault log information . eeprom endurance retention and mass write operation time are specified in the electrical characteristics and absolute maximum ratings sections. write operations at t j > 85 c are possible although the electrical characteristics are not guaranteed and the eeprom retention characteristics may be degraded. read operations performed at junction temperatures between 85 c and 125 c do not degrade the eeprom. the fault logging function, which is useful in debugging system problems that may occur at high temperatures, only writes to fault log-specific eeprom locations (parti - tions). if occasional writes to these registers occur above 85c junction, the slight degradation in the data retention characteristics of the fault log does not undermine the usefulness of the function. it is recommended that the eeprom not be written when the control ic die temperature is greater than 85 c. if the die temperature exceeds 130 c, the LTM4676s control ic disables all eeprom write operations. eeprom write operations are subsequently re-enabled when the die temperature drops below 125c. a dditional i nforma tion an even more detailed account of the operation of the LTM4676 s internal control ic can be perused in the ltc3880 data sheet. be reminded of the differences between the LTM4676 s control ic and the ltc3880, per table 1. operational topics discussed in the ltc3880 data sheet not covered here but are equally applicable to the LTM4676follow: n bus timeout failure. n similarities between pmbus, smbus, and i 2 c 2-wire interface. n the p mbus serial digital interface and timing diagrams . n pmbus data format terminology. n protocols for reading/writing to pmbus registers of the LTM4676/ltc3880 control ics, over i 2 c/smbus. 4676fb for more information www.linear.com/LTM4676 ltm 4676
34 a pplica t ions i n f or m a t ion the ltc3880 data sheet is an essential reference docu- ment for this product. to obtain it go to: www.linear.com/ltc3880 LTM4676 c ontrol ic d ifferences from ltc3880 the LTM4676 control ic is a slightly modified version of the ltc3880; differences between the ltc3880 and the LTM4676s control ic are summarized in table 1. as such, it should stand to reason that the ltc3880 data sheet is a valuable reference document for the LTM4676 user, especially for newcomers to the pmbus suite of commands/command codes ( registers) and working with i 2 c/smbus 2-wire interface. apart from exceptions noted in table 1, the pmbus com- mands codes ( registers) supported by the LTM4676 are identical in scope and data format to that of the ltc3880s. refer to ltc3880s pmbus command summary and pmbus command details data sheet sections for detailed information on the supported command codes. note that the ltc3880 rconfig ( resistor pin-strapable) pins require resistor networks from v dd25 to sgnd, whereas the LTM4676 integrates the top resistors and therefore only requires pull-down ( termination) resistors to sgnd. as a result, the resistor pin-strap tables for the LTM4676 differ from the ltc3880. additionally, the LTM4676s f swphcfg pin-strap options have been slightly modified compared to ltc3880s freq_cfg pin-strap options. refer to tables 2 to 5 in this data sheet for details. the typical LTM4676 application circuit is shown in fig - ure?44 on the back page of this data sheet. external capacitor selection is primarily determined by the maximum load current and output voltage. refer to table 20 for specific external capacitor requirements for particular applications. note that up to nine pull-up resistors are required for proper operation of the LTM4676: ? three for the smbus/i 2 c interface ( the scl, sda, and alert pins); two, only if the system smbus host does not make use of the alert interrupt. ? one each for the run 0 and run 1 pins ( or, just one to run 0 and run 1 , if run 0 and run 1 are electrically connected together). ? one each for gpio 0 and gpio 1 ( or, just one to gpio 0 and gpio 1 , if gpio 0 and gpio 1 are electrically connected together). ? one on share_clk, required, for the LTM4676 to establish a heartbeat time base for timing-related op - erations and functions ( output voltage ramp-up timing, voltage margining transition timing, sync open-drain drive frequency). ? one on sync, in order for the LTM4676 to phase lock to the frequency generated by the open-drain output of its digital engine. exception: in some applications, it is desirable to drive the LTM4676s sync pin with a hard-driven ( low impedance) external clock. this is the only scenario where the LTM4676 does not require a pull-up resistor on sync. however, be aware that the sync pin can be low impedance during nvm ini - tialization, i .e., during download of eeprom contents to ram (for ~50ms [note 12] after sv in power is ap- plied). therefore , the hard-driven clock signal should only be applied to the LTM4676 sync pin through a series resistor whose impedance limits current into the sync pin during nvm initialization to less than 10ma. furthermore, any clock signal should be provided prior to the run n pins toggle from logic low to logic high, or else the switching frequency of the LTM4676 will start off at the low end of its pll-capture range (~225khz) until the sync clock becomes established. 4676fb for more information www.linear.com/LTM4676 ltm 4676
35 a pplica t ions i n f or m a t ion table 1. summary of supported commands and differences between the LTM4676s control ic and the ltc3880 (items of greatest significance indicated by gray-shaded cells; common commands, values and attributes indicated by non-shaded, merged cells) pmbus command name, or feature cmd code (register) command or feature description ltc3880 nvm factory-default value and/or attributes LTM4676 nvm factory-default value and/or attributes freq cfg (or f swphcfg ) pin-strap options n /a switching frequency and phase- angle pin-strap table. look-up table for pin-strapping options on setting channel phase angles and power-up switching frequency is different. freq cfg pin on the ltc3880; f swphcfg pin on the LTM4676. see table 4 of this data sheet. page n 0x00 channel or page currently targeted for paged communications. no difference: 0x00, read/write, non-paged, not stored in nvm. operation n 0x01 operating mode control. on/off, margin high and margin low. no difference: 0x80, read/write, paged, stored in user-editable nvm. on_off_config n 0x02 run n pin and on/off configuration. 0x1e, read/write, paged, stored in user-editable nvm. 0x1f, read/write, paged, stored in user-editable nvm. clear_faults 0x03 clear any fault bits that have been set. no difference: default value not applicable, send byte only, non-paged, not stored in nvm. write_protect 0x10 level of protection provided by the device against accidental changes. no difference: 0x00, read/write, non-paged, stored in user-editable nvm. store_user_all 0x15 store user operating memory to eeprom (user-editable nvm). no difference: default value not applicable, send byte only, non-paged, not stored in nvm. restore_user_ all 0x16 restore user operating memory from eeprom. no difference: default value not applicable, send byte only, non-paged, not stored in nvm. capability 0x19 summary of pmbus optional communication protocols supported by this device. no difference: 0xb0, read-only, non-paged, not stored in nvm. vout_mode n 0x20 output voltage format/exponent. no difference: 0x14 (2 C12 ), read-only, paged, not stored in nvm. vout_command n 0x21 nominal output voltage set point. no difference: 0x1000 (1.000v), read/write, paged, stored in user-editable nvm. vout_max n 0x24 the upper limit on the commandable output voltage. page 0x00: 0x4189 (4.096v). page 0x01: 0x5800 (5.500v). read/write, paged, stored in user- editable nvm. page 0x00: 0x4000 (4.000v). page 0x01: 0x5666 (5.400v). read/write, paged, stored in user- editable nvm. vout_margin_ high n 0x25 margin high output voltage set point. must be greater than vout_command n . no difference: 0x10cd (1.050v), read/write, paged, stored in user-editable nvm. vout_margin_ low n 0x26 margin low output voltage set point. must be less than vout_command n . no difference: 0x0f33 (0.950v), read/write, paged, stored in user-editable nvm. vout_transition_ rate n 0x27 the rate at which the output voltage changes when vout n is commanded to a new value via i 2 c. 0xaa00 (0.25v/ms), read/write, paged, stored in user-editable nvm. 0x8042 (0.001v/ms). read/write, paged, stored in user-editable nvm. frequency_ switch 0x33 the switching frequency setting. 0xfabc (350khz), read/write, non- paged, stored in user-editable nvm. 0xfbe8 (500khz), read/write, non- paged, stored in user-editable nvm. vin_on 0x35 the undervoltage lockout (uvlo)- rising threshold. 0xcb40 (6.5v), as monitored on the ltc3880s v in pin, read/write, non- paged, stored in user-editable nvm. 0xcac0 (5.500v), as monitored on the LTM4676s sv in pin, read/ write, non-paged, stored in user- editable nvm. vin_off 0x36 the undervoltage lockout (uvlo)- falling threshold. 0xcb00 (6.0v) , as monitored on the ltc3880s v in pin, read/write, non- paged, stored in user-editable nvm. 0xcaa0 (5.250v) , as monitored on the LTM4676s sv in pin, read/ write, non-paged, stored in user- editable nvm. 4676fb for more information www.linear.com/LTM4676 ltm 4676
36 a pplica t ions i n f or m a t ion pmbus command name, or feature cmd code (register) command or feature description ltc3880 nvm factory-default value and/or attributes LTM4676 nvm factory-default value and/or attributes iout_cal_gain n 0x38 the ratio of the voltage at the control ics current-sense pins to the sensed current, in m, at 25c. 1.8m, read/write, paged, stored in user-editable nvm. trimmed at ate , read-only, stored in factory-only nvm. vout_ov_fault_ limit n 0x40 output overvoltage fault limit. no difference: 0x119a (1.100v), read/write, paged, stored in user-editable nvm. vout_ov_fault_ response n 0x41 action to be taken by the device when an output overvoltage fault is detected. no difference: 0xb8 (non-latching shutdown; autonomous restart upon fault removal), read/write, paged, stored in user-editable nvm. vout_ov_warn_ limit n 0x42 output overvoltage warning threshold. 0x1133 (1.075v), read/write, paged, stored in user-editable nvm. 0x111f (1.070v), read/write, paged, stored in user-editable nvm. vout_uv_warn_ limit n 0x43 output undervoltage warning threshold. 0x0ecd (0.925v), read/write, paged, stored in user-editable nvm. 0x0ee1 (0.930v), read/write, paged, stored in user-editable nvm. vout_uv_fault_ limit n 0x44 output undervoltage fault limit. no difference: 0x0e66 (0.900v), read/write, paged, stored in user-editable nvm. vout_uv_fault_ response n 0x45 action to be taken by the device when an output undervoltage fault is detected. no difference: 0xb8 (non-latching shutdown; autonomous restart upon fault removal), read/write, paged, stored in user-editable nvm. iout_oc_fault_ limit n 0x46 output overcurrent fault threshold (cycle-by-cycle inductor peak current). 0xdbb8 (29.75a), read/write, paged, stored in user-editable nvm. 0xdadb (22.84a), read/write, paged, stored in user-editable nvm. iout_oc_fault_ response n 0x47 action to be taken by the device when an output overcurrent fault is detected. no difference: 0x00 (try to regulate through the fault condition/event; limit the cycle-by-cycle peak of the inductor current to not exceed the commanded iout_oc_fault_limit), read/write, paged, stored in user-editable nvm. iout_oc_warn_ limit n 0x4a output overcurrent warning threshold (time-averaged inductor current). 0xda80 (20.00a), read/write, paged, stored in user-editable nvm. 0xd3e6 (15.59a), read/write, paged, stored in user-editable nvm. ot_fault_limit n 0x4f overtemperature fault threshold. 0xeb20 (100c), read/write, paged, stored in user-editable nvm. 0xf200 (128c), read/write, paged, stored in user-editable nvm. ot_fault_ response n 0x50 action to be taken by the device when an overtemperature fault is detected via tsns na (tsnsn). no difference: 0xb8 (non-latching shutdown; autonomous restart upon fault removal), read/write, paged, stored in user-editable nvm. ot_warn_limit n 0x51 overtemperature warning threshold. 0xeaa8 (85c), read/write, paged, stored in user-editable nvm. 0xebe8 (125c), read/write, paged, stored in user-editable nvm. ut_fault_limit n 0x53 undertemperature fault threshold. 0xe580 (C40c), read/write, paged, stored in user-editable nvm. 0xe530 (C45c), read/write, paged, stored in user-editable nvm. ut_fault_ response n 0x54 response to undertemperature fault events. 0xb8 (non-latching shutdown; autonomous restart upon fault removal), read/write, paged, stored in user-editable nvm. 0x00 (ignore; continue without interruption), read/write, paged, stored in user-editable nvm, read/ write, paged, stored in user-editable nvm. vin_ov_fault_ limit 0x55 input supply (sv in ) overvoltage fault limit. 0xd3e0 (15.5v), read/write, non- paged, stored in user-editable nvm. 0xdb60 (27.0v), read/write, non- paged, stored in user-editable nvm. vin_ov_fault_ response n 0x56 response to input overvoltage fault events. 0x80 (latched-off shutdown), read/ write, paged, stored in user-editable nvm. 0xb8 (non-latching shutdown; autonomous restart upon fault removal), read/write, paged, stored in user-editable nvm. vin_uv_warn_ limit 0x58 input undervoltage warning threshold. 0xcb26 (6.297v), read/write, non- paged, stored in user-editable nvm. 0xcaa6 (5.297v), read/write, non- paged, stored in user-editable nvm. 4676fb for more information www.linear.com/LTM4676 ltm 4676
37 a pplica t ions i n f or m a t ion pmbus command name, or feature cmd code (register) command or feature description ltc3880 nvm factory-default value and/or attributes LTM4676 nvm factory-default value and/or attributes iin_oc_warn_ limit 0x5d input supply overcurrent warning threshold. 0xd280 (10a), read/write, non- paged, stored in user-editable nvm. 0xd300 (12a), read/write, non- paged, stored in user-editable nvm. power_good_on n 0x5e output voltage at or above which a power good should be asserted. no difference: 0x0ee1 (0.9299v), read/write, paged, stored in user-editable nvm. power_good_off n 0x5f output voltage at or below which a power good should be de-asserted. no difference: 0x0eb8 (0.9199v), read/write, paged, stored in user-editable nvm. ton_delay n 0x60 time from run n and/or operation n on to output rail turn-on. no difference: 0x8000 (0ms), read/write, paged, stored in user-editable nvm. ton_rise n 0x61 time from when the output voltage reference starts to rise until it reaches its commanded setting. 0xd200 (8ms), read/write, paged, stored in user-editable nvm. 0xc300 (3ms), read/write, paged, stored in user-editable nvm. ton_max_fault_ limit n 0x62 turn-on watchdog timeout fault threshold (time permitted for vout n to reach or exceed vout_ uv_fault_limit n after turn-on command is received). 0xd280 (10ms), read/write, paged, stored in user-editable nvm. 0xca80 (5ms), read/write, paged, stored in user-editable nvm. ton_max_fault_ response n 0x63 action to be taken by the device when a ton_max_fault n event is detected. no difference: 0xb8 (non-latching shutdown; autonomous restart upon fault removal), read/write, paged, stored in user-editable nvm. toff_delay n 0x64 time from run and/or operation off to the start of toff_fall n ramp. no difference: 0x8000 (0ms), read/write, paged, stored in user-editable nvm. toff_fall n 0x65 time from when the output voltage reference starts to fall until it reaches 0v. 0xd200 (8ms), read/write, paged, stored in user-editable nvm. 0xc300 (3ms), read/write, paged, stored in user-editable nvm. toff_max_warn_ limit n 0x66 turn-off watchdog timeout fault threshold (time permitted for vout n to decay to or below 12.5% of the commanded vout n value at the time of receiving a turn-off command). 0xf258 (150ms), read/write, paged, stored in user-editable nvm. 0x8000 (no limit; warning is disabled ), read/write, paged, stored in user-editable nvm. status_by te n 0x78 one byte summary of the units fault condition. no difference: default value not applicable, read/write, paged, not stored in nvm. status_word n 0x79 tw o byte summary of the units fault condition. no difference: default value not applicable, read/write, paged, not stored in nvm. status_vout n 0x7a output voltage fault and warning status. no difference: default value not applicable, read/write, paged, not stored in nvm. status_iout n 0x7b output current fault and warning status. no difference: default value not applicable, read/write, paged, not stored in nvm. status_input 0x7c input supply (sv in ) fault and warning status. no difference: default value not applicable, read/write, non-paged, not stored in nvm. status_ temperature n 0x7d tsns na (tsnsn)-sensed temperature fault and warning status for read_temerature_1 n . no difference: default value not applicable, read/write, paged, not stored in nvm. status_cml 0x7e communication and memory fault and warning status. no difference: default value not applicable, read/write, non-paged, not stored in nvm. status_mfr_ specific n 0x80 manufacturer specific fault and state information. no difference: default value not applicable, read/write, paged, not stored in nvm. 4676fb for more information www.linear.com/LTM4676 ltm 4676
38 pmbus command name, or feature cmd code (register) command or feature description ltc3880 nvm factory-default value and/or attributes LTM4676 nvm factory-default value and/or attributes read_vin 0x88 measured input supply (sv in ) voltage. no difference: default value not applicable, read-only, non-paged, not stored in nvm. read_iin 0x89 calculated total input supply current. no difference: default value not applicable, read-only, non-paged, not stored in nvm. read_vout n 0x8b measured output voltage. no difference: default value not applicable, read-only, paged, not stored in nvm. read_iout n 0x8c measured output current. no difference: default value not applicable, read-only, paged, not stored in nvm. read_ temperature_1 n 0x8d measurement of tsns na (tsnsn)- sensed temperature. no difference: default value not applicable, read-only, paged, not stored in nvm. read_ temperature2 n 0x8e measured control ic junction temperature. no difference: default value not applicable, read-only, paged, not stored in nvm. read_duty_ cycle n 0x94 measured duty cycle of mt n . no difference: default value not applicable, read-only, paged, not stored in nvm. read_pout n 0x96 measured output power. no difference: default value not applicable, read-only, paged, not stored in nvm. pmbus_revision 0x98 pmbus revision supported by this device. no difference: 0x11 (revision 1.1 of part i and revision 1.1 of part ii of pmbus specification documents), read-only, non-paged, not stored in nvm. mfr_id 0x99 manufacturer identification, in ascii no difference: lt c , read-only, non-paged. mfr_model 0x9a manufacturers part number, in ascii ltc3880, read-only, non-paged. LTM4676, read-only, non-paged. mfr_serial 0x9e serial number of this specific unit. no difference: up to nine bytes of custom-formatted data that identify the units configuration, read-only, non-paged. mfr_vout_max 0xa5 maximum allowed output voltage. no difference: 0x4189 (4.096v) on channel 0, 0x5800 (5.500v) on channel 1. read/write, paged, not stored in user-editable nvm. user _data_00 0xb0 oem reserved data. read/write, non-paged, stored in user-editable nvm. recommended against altering. read/write, non-paged, stored in user-editable nvm. recommended against altering. user_data_01 n 0xb1 oem reserved data. read/write, paged, stored in user- editable nvm. recommended against altering. read/write, paged, stored in user- editable nvm. recommended against altering. user_data_02 0xb2 oem reserved data. read/write, non-paged, stored in user-editable nvm. recommended against altering. read/write, non-paged, stored in user-editable nvm. recommended against altering. user_data_03 n 0xb3 user-editable words available for the user. no difference: 0x0000, read/write, paged, stored in user-editable nvm. user_data_04 0xb4 a user-editable word available for the user. no difference: 0x0000, read/write, non-paged, stored in user-editable nvm. mfr_ee_erase 0xbd unlock user eeprom for access by mfr_ee_erase and mfr_ee_ data commands. no difference: default value not applicable, read/write, non-paged, not stored in nvm. mfr_ee_erase 0xbe initialize user eeprom for bulk programming by mfr_ee_ data . no difference: default value not applicable, read/write, non-paged, not stored in nvm. a pplica t ions i n f or m a t ion 4676fb for more information www.linear.com/LTM4676 ltm 4676
39 pmbus command name, or feature cmd code (register) command or feature description ltc3880 nvm factory-default value and/or attributes LTM4676 nvm factory-default value and/or attributes mfr_ee_ data 0xbf data transferred to and from eeprom using sequential pmbus word reads or writes. supports bulk programming. no difference: default value not applicable, read/write, non-paged, not stored in nvm. mfr_chan_ config_* n 0xd0 channel-specific configuration bits. 0x1f, read/write, paged, stored in user-editable nvm. register is named mfr_chan_config_ lt c 3880. 0x1f, read/write, paged, stored in user-editable nvm. register is named mfr_chan_config and referred to as mfr_chan_config_ ltm467x in ltpowerplay. mfr_ config_ all _* 0xd1 global configuration bits, i.e., common to both v out channels 0 and 1. 0x09, read/write, non-paged, stored in user-editable nvm. register is named mfr_config_all_ lt c 3880. 0x09, read/write, non-paged, stored in user-editable nvm. register is named mfr_config_all and referred to as mfr_config_all_ ltm467x in ltpowerplay. mfr_gpio_ propagate_* n 0xd2 configuration bits for propagating faults to the gpio n pins. 0x2997, read/write, paged, stored in user-editable nvm. register is named mfr_gpio_propagate_ lt c 3880. 0x6893, read/write, paged, stored in user-editable nvm. register is named mfr_gpio_propagate and referred to as mfr_gpio_ propagate_ltm467x in ltpowerplay. mfr_pwm_ mode_* n 0xd4 configuration for the pwm engine of each v out channel. 0xc2, read/write, paged, stored in user-editable nvm. bit 3 is reserved and should be 0b. register is named mfr_pwm_mode_ lt c 3880. 0xc2, read/write, paged, stored in user-editable nvm. when bit 3 of page 0 (mfr_pwm_mode_ LTM4676 0 [3]) is 0 b , channel temperature-sensing is performed per ltc3880 documentation. when mfr_pwm_mode_LTM4676 0 [3]= 1 b , t sns1a monitors a temperature sensor external to the LTM4676, per the operation section. register is named mfr_pwm_mode and referred to as mfr_pwm_mode_ ltm467x in ltpowerplay. mfr_gpio_ response n 0xd5 action to be taken by the device when the gpio n pin is asserted low by circuitry external to the unit. no difference: 0xc0 (make the respective outputs power stage high impedance, i.e., three-stated; autonomous restart upon fault removal), read/write, paged, stored in user-editable nvm. mfr _ot_fault_ response 0xd6 action to be taken by the device when a control ic junction overtemperature fault is detected. no difference: 0xc0 (make the respective outputs power stage high impedance, i.e., three-stated; autonomous restart upon fault removal), read/write, non-paged, stored in user-editable nvm. mfr _iout_peak n 0xd7 maximum measured value of read_iout n since the last mfr_ clear_peaks. no difference: default value not applicable, read-only, paged, not stored in nvm. mfr_channel_ address n 0xd8 address to the page n -activated channel. no difference: 0x80, read/write, paged, stored in user-editable nvm. a pplica t ions i n f or m a t ion 4676fb for more information www.linear.com/LTM4676 ltm 4676
40 pmbus command name, or feature cmd code (register) command or feature description ltc3880 nvm factory-default value and/or attributes LTM4676 nvm factory-default value and/or attributes mfr_retry_ delay n 0xdb retry interval during fault-retry mode. 0xfabc (350ms), read/write, paged, stored in user-editable nvm. 0xf3e8 (250ms), read/write, paged, stored in user-editable nvm. mfr_restart_ delay n 0xdc minimum interval (nominal) the run n pin is pulled logic low by internal circuitry. 0xfbe8 (500ms), read/write, paged, stored in user-editable nvm. 0xf258 (150ms), read/write, paged, stored in user-editable nvm. mfr_vout_peak n 0xdd maximum measured value of read_vout n since the last mfr_ clear_peaks. no difference: default value not applicable, read-only, paged, not stored in nvm. mfr_vin_peak 0xde maximum measured value of read_vin since the last mfr_ clear_peaks. no difference: default value not applicable, read-only, non-paged, not stored in nvm. mfr_ temperature_1_ peak n 0xdf maximum value of tsns na (tsnsn)- measured temperature since the last mfr_clear_peaks. no difference: default value not applicable, read-only, paged, not stored in nvm. mfr_clear_peaks 0xe3 clears all peak values. no difference: default value not applicable, send byte only, non-paged, not stored in nvm. mfr_p ads 0xe5 digital status of the i/o pads. no difference: default value not applicable, read-only, non-paged, not stored in nvm. mfr_address 0xe6 the 7 bits of the LTM4676s i 2 c slave address. 0x4f, read/write, non-paged, stored in user-editable nvm. least significant four bits augmented by asel resistor network. can take on value 0x80 to disable device-specific addressing. 0x4f, read-only, non-paged, stored in factory-only nvm. least significant four bits augmented by asel resistor pin-strap. cannot take on value 0x80; device-specific addressing cannot be disabled. mfr_special_id 0xe7 manufacturer code representing ic silicon and revision 0x40xx, read-only, non-paged. 0x440x, read-only, non-paged. mfr_iin_offset n 0xe9 coefficient used in calculations of read_iin and mfr_read_iin n , representing the contribution of input current drawn by the control ic, including the mosfet drivers. 0x9333 (0.0500a), read/write, paged, stored in user-editable nvm. 0x8be7 (0.0305a), read/write, paged, stored in user-editable nvm. mfr_fault_log_ store 0xea commands a transfer of the fault log from ram to eeprom. this causes the part to behave as if a channel has faulted off. no difference: default value not applicable, send byte only, non-paged, not stored in nvm. mfr_fault_log_ clear 0xec initialize the eeprom block reserved for fault logging and clear any previous fault logging locks. no difference: default value not applicable, send byte only, non-paged, not stored in nvm. a pplica t ions i n f or m a t ion 4676fb for more information www.linear.com/LTM4676 ltm 4676
41 pmbus command name, or feature cmd code (register) command or feature description ltc3880 nvm factory-default value and/or attributes LTM4676 nvm factory-default value and/or attributes mfr_read_iin n 0xed calculated input current, by channel. no difference: default value not applicable, read-only, paged, not stored in nvm. mfr_fault_log 0xee fault log data bytes. this sequentially retrieved data is used to assemble a complete fault log. no difference: default value not applicable, read-only, non-paged, stored in fault-log nvm. mfr_common 0xef manufacturer status bits that are common across multiple lt c ics/ modules. no difference: default value not applicable, read-only, non-paged, not stored in nvm. mfr_compare_ user_all 0xf0 compares current command contents (ram) with nvm. no difference: default value not applicable, send byte only, non-paged, not stored in nvm. mfr_ temperature_2_ peak 0xf4 maximum measured control ic junction temperature since last mfr_clear_peaks. no difference: default value not applicable, read-only, non-paged, not stored in nvm. mfr_pwm_ config_* 0xf5 configuration bits for setting the phase interleaving angles and output voltage ranges of channels 0 and 1, and share_clk behavior in uvlo. 0x10, read/write, non-paged, stored in user-editable nvm. register is named mfr_pwm_config_ lt c 3880. 0x10, read/write, non-paged, stored in user-editable nvm. register is named mfr_pwm_config and referred to as mfr_pwm_config_ ltm467x in ltpowerplay. mfr_iout_cal_ gain_tc n 0xf6 temperature coefficient of the current sensing element. 0x0f3c (3900ppm/c), read/write, paged, stored in user-editable nvm. 0x0f14 (3860ppm/c), read/write, paged, stored in user-editable nvm. mfr_temp_1_ gain n 0xf8 sets the slope of the temperature sensors that interface to tsns na (tsnsn). no difference: 0x4000 (1.0, in custom units), read/write, paged, stored in nvm. mfr_temp_1_ offset n 0xf9 sets the offset of the tsns na (tsnsn) temperature sensor with respect to C273.1c. no difference: 0x8000 (0.0), read/write, paged, stored in nvm. mfr_rail_ address n 0 xfa common address for polyphase outputs to adjust common parameters. no difference: 0x80, read/write, paged, stored in nvm. mfr_reset 0xfd commanded reset without requiring a power down. no difference: default value not applicable, send byte only, non-paged, not stored in nvm. a pplica t ions i n f or m a t ion 4676fb for more information www.linear.com/LTM4676 ltm 4676
42 a pplica t ions i n f or m a t ion table 2. v outn cfg pin strapping look-up table for the LTM4676's output voltage, coarse setting (not applicable if mfr_config_all[6] = 1 b ) r voutn cfg * (k) v outn (v) setting coarse mfr_pwm_config[6- n ] bit open nvm nvm 32.4 see table 3 see table 3 22.6 3.3 0 18.0 3.1 0 15.4 2.9 0 12.7 2.7 0 10.7 2.5 0, if v trimn > 0mv 1, if v trimn 0mv 9.09 2.3 1 7.68 2.1 1 6.34 1.9 1 5.23 1.7 1 4.22 1.5 1 3.24 1.3 1 2.43 1.1 1 1.65 0.9 1 0.787 0.7 1 0 0.5 1 *r voutn cfg value indicated is nominal. select r voutn cfg from a resistor vendor such that its value is always within 3% of the value indicated in the table. take into account resistor initial tolerance, t.c.r. and resistor operating temperatures, soldering heat/ir reflow, and endurance of the resistor over its lifetime. thermal shock/cycling, moisture (humidity) and other effects (depending on ones specific application) could also affect r voutn cfg s value over time. all such effects must be taken into account in order for resistor pin strapping to yield the expected result at every sv in power-up and/or every execution of mfr_reset, over the lifetime of ones product. table 3. v trimn cfg pin strapping look-up table for the LTM4676's output voltage, fine adjustment setting (not applicable if mfr_config_all[6] = 1 b ) r vtrim n cfg * (k) v trim (mv) fine adjustment to v outn setting when respective r voutn cfg 32.4k v outn output voltage setting (v) when v outn cfg pin uses r cfg = 32.4k mfr_pwm_ config[6-n ] bit open 0 nvm 0, if vout_ov_ fault_limit n > 2.75v 1, if vout_ov_ fault_limit n 2.75v 32.4 99 22.6 86.625 18.0 74.25 15.4 61.875 12.7 49.5 10.7 37.125 5.50 0 9.09 24.75 5.25 0 7.68 12.375 5.00 0 6.34 C12.375 4.75 0 5.23 C24.75 4.50 0 4.22 C37.125 4.25 0 3.24 C49.5 4.00 0 2.43 C61.875 3.75 0 1.65 C74.25 3.63 0 0.787 C86.625 3.50 0 0 C99 3.46 0 * r vtrimn cfg value indicated is nominal. select r vtrimn cfg from a resistor vendor such that its value is always within 3% of the value indicated in the table. take into account resistor initial tolerance, t.c.r. and resistor operating temperatures, soldering heat/ir reflow, and endurance of the resistor over its lifetime. thermal shock/cycling, moisture (humidity) and other effects (depending on ones specific application) could also affect r vtrimn cfg s value over time. all such effects must be taken into account in order for resistor pin strapping to yield the expected result at every sv in power-up and/or every execution of mfr_reset, over the lifetime of ones product. 4676fb for more information www.linear.com/LTM4676 ltm 4676
43 a pplica t ions i n f or m a t ion table 4. f swphcfg pin strapping look- up table to set the LTM4676 's switching frequency and channel phase- interleaving angle (not applicable if mfr_config_all[6] = 1 b ) r fswphcfg * (k) switching frequency (khz) sync to 0 sync to 1 bits [2:0] of mfr_pwm_config open nvm; LTM4676 default = 500 nvm; LTM4676 default = 180 nvm; LTM4676 default = 0 nvm; LTM4676 default = 000 b 32.4 250 0 180 000 b 22.6 350 0 180 000 b 18.0 425 0 180 000 b 15.4 575 0 180 000 b 12.7 650 0 180 000 b 10.7 750 0 180 000 b 9.09 1000 0 180 000 b 7.68 500 120 240 100 b 6.34 500 90 270 001 b 5.23 external** 0 240 010 b 4.22 external** 0 120 011 b 3.24 external** 60 240 101 b 2.43 external** 120 300 110 b 1.65 external** 90 270 001 b 0.787 external** 0 180 000 b 0 external** 120 240 100 b *r fswphcfg value indicated is nominal. select r fswphcfg from a resistor vendor such that its value is always within 3% of the value indicated in the table. take into account resistor initial tolerance, t.c.r. and resistor operating temperatures, soldering heat/ir reflow, and endurance of the resistor over its lifetime. thermal shock/cycling, moisture (humidity) and other effects (depending on ones specific application) could also affect r fswphcfg s value over time. all such effects must be taken into account in order for resistor pin-strapping to yield the expected result at every sv in power-up and/or every execution of mfr_reset, over the lifetime of ones product. **"external" setting corresponds to frequency_switch (register 0x33) value set to 0x0000; the device synchronizes its switching frequency to that of the clock provided on the sync pin. 4676fb for more information www.linear.com/LTM4676 ltm 4676
44 a pplica t ions i n f or m a t ion table 5. asel pin strapping look-up table to set the LTM4676's slave address (applicable regardless of mfr_config_all[6] setting) r asel * (k) slave address open 100_1111_r/w 32.4 100_1111_r/w 22.6 100_1110_r/w 18.0 100_1101_r/w 15.4 100_1100_r/w 12.7 100_1011_r/w 10.7 100_1010_r/w 9.09 100_1001_r/w 7.68 100_1000_r/w 6.34 100_0111_r/w 5.23 100_0110_r/w 4.22 100_0101_r/w 3.24 100_0100_r/w 2.43 100_0011_r/w 1.65 100_0010_r/w 0.787 100_0001_r/w 0 100_0000_r/w where: r/w = read/write bit in control byte. all pmbus device addresses listed in the specification are 7 bits wide unless other wise noted. note: the LTM4676 will always respond to slave address 0x5a and 0x5b regardless of the nvm or asel resistor configuration values. *r cfg value indicated is nominal. select r cfg from a resistor vendor such that its value is always within 3% of the value indicated in the table. take into account resistor initial tolerance, t.c.r. and resistor operating temperatures, soldering heat/ir reflow, and endurance of the resistor over its lifetime. thermal shock cycling, moisture (humidity) and other effects (depending on ones specific application) could also affect r cfg s value over time. all such effects must be taken into account in order for resistor pin-strapping to yield the expected result at every sv in power-up and/or every execution of mfr_reset, over the lifetime of ones product. table 6. LTM4676 mfr_address command examples expressed in 7- and 8-bit addressing description hex device address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w 7 bit 8 bit rail 4 0x5a 0xb4 0 1 0 1 1 0 1 0 0 global 4 0x5b 0xb6 0 1 0 1 1 0 1 1 0 default 0x4f 0x9e 0 1 0 0 1 1 1 1 0 example 1 0x40 0x80 0 1 0 0 0 0 0 0 0 example 2 0x41 0x82 0 1 0 0 0 0 0 1 0 disabled 2,3 1 0 0 0 0 0 0 0 0 note 1: this table can be applied to the mfr_channel_address n and mfr_rail_address n commands, but not the mfr_address command. note 2: a disabled value in one command does not disable the device, nor does it disable the global address. note 3: a disabled value in one command does not inhibit the device from responding to device addresses specified in other commands. note 4: it is not recommended to write the value 0x00, 0x0c (7 bit), or 0x5a (7 bit) or 0x5b (7 bit) to the mfr_channel_address n or the mfr_rail_address n commands. 4676fb for more information www.linear.com/LTM4676 ltm 4676
45 a pplica t ions i n f or m a t ion v in to v out s tep -d own r atios there are restrictions in the maximum v in and v out step- down ratio that can be achieved for a given input voltage. each output of the LTM4676 is capable of 95% duty cycle at 500 khz, but the v in to v out minimum dropout is still a function of its load current and will limit output current capability related to high duty cycle on the topside switch. minimum on-time t on(min) is another consideration in operating at a specified duty cycle while operating at a certain frequency due to the fact that t on(min) < d/f sw , where d is duty cycle and f sw is the switching frequency. t on(min) is specified in the electrical parameters as 90ns. see note 6 in the electrical characteristics section for output current guideline. i nput c ap acitors the LTM4676 module should be connected to a low ac- impedance dc source. for the regulator input four 22f input ceramic capacitors are used to handle the rms ripple current . a 47 f to 100 f surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. this bulk input capacitor is only needed if the input source impedance is compromised by long in- ductive leads , traces or not enough source capacitance. if low impedance power planes are used, then this bulk capacitor is not needed. for a buck converter, the switching duty-cycle can be estimated as: d n = v out n v in n without considering the inductor current ripple, for each output, the rms current of the input capacitor can be estimated as: i cin n (rms) = i out n (max) % ? d n ? 1 ? d n ( ) in the above equation, m % is the estimated efficiency of the power module. the bulk capacitor can be a switcher-rated electrolytic aluminum capacitor, or a polymer capacitor. o utput c ap acitors the LTM4676 is designed for low output voltage ripple noise and good transient response. the bulk output capacitors defined as c out are chosen with low enough effective series resistance ( esr) to meet the output volt- age ripple and transient requirements. c out can be a low esr tantalum capacitor, a low esr polymer capacitor or ceramic capacitor. the typical output capacitance range for each output is from 400 f to 700 f. additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spikes is required. table 20 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 6.5 a/s transient. the table optimizes total equivalent esr and total bulk capacitance to optimize the transient performance. stability criteria are considered in the table 20 matrix, and the linear technology module power design tool will be provided for stability analysis. multiphase operation reduces effective output ripple as a function of the number of phases. application note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. the linear technology module power design tool can calculate the output ripple reduc - tion as the number of implemented phases increases by n times. a small value 10 ? resistor can be placed in series from v outn to the v osns0 + or v osns1 pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. l ight l oad c urrent o pera tion the LTM4676 has three modes of operation including high efficiency burst mode operation, discontinuous conduction mode or forced continuous conduction mode. mode selection is done using the mfr_pwm_mode n command ( discontinuous conduction is always the start- up mode, forced continuous is the default running mode). 4676fb for more information www.linear.com/LTM4676 ltm 4676
46 a pplica t ions i n f or m a t ion in burst mode operation, the peak current in the inductor is set to approximately one- third of the maximum sense voltage even though the voltage on the i th pin indicates a lower value. if the average inductor current is higher than the load current, the error amplifier, ea, will decrease the voltage on the i th pin. when the i th voltage drops below approximately 0.5v , the internal burst mode operation asserts and both power stage mosfets are turned off. in burst mode operation, the load current is supplied by the output capacitor. as the output voltage decreases, the ea output begins to rise. when the output voltage drops sufficiently, burst mode operation is deasserted, and the controller resumes normal operation by turning on the top mosfet (mtn ) on the next pwm cycle. if a channel is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator, i rev , turns off the bottom mosfet (mbn ) just before the inductor current reaches zero, preventing it from reversing and going negative. thus, the controller can operate in discontinuous (pulse-skippng) operation. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined solely by the voltage on the i th pin. in this mode, the efficiency at light loads is lower than in burst mode operation. however, continuous mode exhibits lower output ripple and less interference with audio circuitry. forced continuous conduction mode may result in reverse inductor current, which can cause the input supply to boost. the vin_ov_fault_limit can detect this ( if sv in is connected to v in0 and/or v in1 ) and turn off the offend- ing channel . however, this fault is based on an adc read and can nominally take up to 100 ms to detect. if there is a concern about the input supply boosting, keep the part in discontinuous conduction or burst mode operation. if the part is set to burst mode operation, as the inductor average current increases, the controller automatically modifies the operation from burst mode operation, to discontinuous mode to continuous mode. s witching f requency and p hase the switching frequency of the LTM4676s channels is established by its analog phase- locked- loop ( pll) locking on to the clock present at the modules sync pin. the clock waveform on the sync pin can be generated by the LTM4676s internal circuitry when an external pull-up resistor to 3.3v ( e.g., v dd33 ) is provided, in combination with the LTM4676 control ics frequency_switch register being set to one of the following supported values : 250khz, 350khz, 425khz, 500khz, 575khz, 650khz, 750khz, 1mhz ( see table 8 for hexadecimal values). in this configuration, the module is called a sync master: sync becomes a bidirectional open-drain pin, and the LTM4676 pulls sync logic low for nominally 500 ns at a time, at the prescribed clock rate. the sync signal can be bused to other LTM4676 modules ( configured as sync slaves), for purposes of synchronizing switching frequencies of multiple modules within a systembut only one LTM4676 should be configured as a sync master; the other LTM4676(s) should be configured as sync slaves. to configure an LTM4676 as a sync slave, set its frequency_switch register to 0 x0000. in that configuration, the LTM4676s sync pin becomes a high impedance input, onlyi.e., it does not drive sync low. the frequency_ switch register can be altered via i 2 c commands, but only when switching action is disengaged, i.e., the modules outputs are turned off. the frequency_switch register takes on the value stored in nvm at sv in power-up, but is overridden according to a resistor pin- strap applied between the f swphcfg pin and sgnd only if the module is configured to respect resistor pin-strap settings (mfr_config_all[6] = 0 b ). table 4 highlights available resistor pin-strap and corresponding frequency_switch settings. the relative phasing of all active channels in a polyphase ? rail should be optimally phased. the relative phasing of each rail is 360/ n, where n is the number of phases in the rail. mfr_pwm_config[2:0] configures channel relative phasing with respect to the sync pin. phase 4676fb for more information www.linear.com/LTM4676 ltm 4676
47 a pplica t ions i n f or m a t ion relationship values are indicated with 0 corresponding to the falling edge of sync being coincident with the turn-on of the top mosfets, mtn. the mfr_pwm_config register can be altered via i 2 c commands, but only when switching action is disengaged, i.e., the modules outputs are turned off. the mfr_pwm_config register takes on the value stored in nvm at sv in power-up, but is overridden according to a resistor pin-strap applied between the f swphcfg pin and sgnd only if the module is configured to respect resistor pin-strap settings (mfr_config_all[6] = 0 b ). table 4 highlights available resistor pin-strap and corresponding mfr_pwm_config[2:0] settings. some combinations of frequency _ switch and mfr_pwm_config[2:0] are not available by resistor pin - strapping the f swphcfg pin. all combinations of supported values for frequency_ switch and mfr_pwm_config[2:0] can be configured by nvm programmingor, i 2 c transactions, provided switching action is disengaged, i.e., the modules outputs are turned off. care must be taken to minimize capacitance on sync to assure that the pull-up resistor versus the capacitor load has a low enough time constant for the application to form a clean clock . (see open-drain pins, later in this section.) when an LTM4676 is configured as a sync slave, it is permissible for external circuitry to drive the sync pin from a current-limited source ( less than 10 ma), rather than using a pull-up resistor. any external circuitry must not drive high with arbitrarily low impedance at sv in power- up, because the sync output can be low impedance until nvm contents have been downloaded to ram. recommended LTM4676 switching frequencies of operation for many common v in -to-v out applications are indicated in table 7. when the two channels of an LTM4676 are stepping input voltage(s) down to output voltages whose recommended switching frequencies in table 7 are significantly different, operation at the higher of the two recommended switching frequencies is preferable, but minimum on-time must be considered. (see minimum on-time considerations section.) for example, consider an application in which it is desired for an LTM4676 to step-down 12v in to 1 v out on channel 0, and 12v in to 3.3v out on channel 1: according to table?7, the recommended switching frequency is 350 khz and 650khz, respectively. however, the switching frequency setting of the LTM4676 is common to both channels. based on the aforementioned guidance, operation at 650khz would be preferredin order to keep inductor ripple currents reasonablehowever, it is then realized that the on- time for a 12v in - to-1v out condition at 650khz is only 128 ns, which is marginal. therefore, for this particular example, the recommended switching frequency becomes 575khz. table 7. recommended switching frequency for various v in -to-v out step-down scenarios. 5v in 8v in 12v in 24v in 0.9v out 350khz 350khz 350khz 250khz 1.0v out 350khz 350khz 350khz 250khz 1.2v out 350khz 350khz 350khz 350khz 1.5v out 350khz 350khz 425khz 425khz 1.8v out 425khz 425khz 500khz 500khz 2.5v out 425khz 500khz 575khz 650khz 3.3v out 425khz 575khz 650khz 750khz 5.0v out n/a 500khz 750khz 1mhz the current drawn by the sv in pin of the LTM4676 is not digitized or computed. a value representing the estimated sv in current is located in the mfr_iin_offset n register, and is used in the computations of input current readback telemetry, namely read_iin and and mfr_read_iin n . the recommended setting of mfr_ iin_ offset n is found in table 8. the same value should be used for mfr_iin_offset 0 and mfr_iin_offset 1 ( i.e., pages 0x00 and 0x01). 4676fb for more information www.linear.com/LTM4676 ltm 4676
48 a pplica t ions i n f or m a t ion table 8. recommended mfr_iin_offset n setting vs switching frequency setting switching frequency (khz) frequency_ switch register value (hex.) recommended mfr_iin_ offset n setting (ma) recommended mfr_iin_ offset n setting (hex.) 250 0xf3e8 20.3 0x8a99 350 0xfabc 24.4 0x8b20 425 0xfb52 27.4 0x8b82 500 0xfbe8 30.5 0x8be7 575 0x023f 33.6 0x9227 650 0x028a 36.7 0x9259 750 0x02ee 40.8 0x929c 1000 0x03e8 51.0 0x9344 sync. to external clock, f sync 0x0000 0.041 ? f sync + 10.037 * *see ltc3880 data sheet, l11 data format. m inimum o n -t ime c onsiderations minimum on-time, t on(min) , is the smallest time duration that the LTM4676 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t on(min) < v out n v in n ? f osc if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the LTM4676 is 90 ns, nominal, guardband to 130ns. v ariable d ela y t ime , s of t -s t art and o utput v ol tage r amping the LTM4676 must enter its run state prior to soft-start. the run n pins are released after the part initializes and sv in is greater than the vin_on threshold. if multiple LTM4676s are used in an application, they should be configured to share the same run n pins. they all hold their respective run n pins low until all devices initialize and sv in exceeds the vin_on threshold for all devices. the share_clk pin assures all the devices connected to the signal use the same time base. after the run n pin releases, the controller waits for the user- specified turn- on delay ( ton_ delay n ) prior to initiating an output voltage ramp. multiple LTM4676s and other ltc parts can be configured to start with variable delay times. to work correctly, all devices use the same timing clock ( share_clk) and all devices must share the run n pin. this allows the relative delay of all parts to be synchronized. the actual variation in the delay will be dependent on the highest clock rate of the devices connected to the share_clk pin ( all linear technology ics are configured to allow the fastest share_clk signal to control the timing of all devices). the share_ clk signal can be 7.5% in frequency, thus the actual time delays will have some variance. soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0 v to the commanded voltage set point. the rise time of the voltage ramp can be programmed using the ton_rise n command to minimize inrush currents associated with the start-up voltage ramp. the soft-start feature is disabled by setting ton_rise n to any value less than 0.250ms. the LTM4676 performs the necessary math internally to assure the voltage ramp is controlled to the desired slope. however, the voltage slope can not be any faster than the fundamental limits of the power stage. the number of steps in the ramp is equal to ton_rise/0.1ms. therefore, the shorter the ton_rise n time setting, the more jagged the soft-start ramp appears. the LTM4676 pwm always operates in discontinuous mode during the ton_rise n operation. in discontinuous mode, the bottom mosfet (mbn ) is turned off as soon as reverse current is detected in the inductor. this allows the regulator to start up into a pre-biased load. there is no analog tracking feature in the LTM4676; however, two outputs can be given the same ton _ rise n and ton_delay n times to achieve ratiometric rail tracking. because the run n pins are released at the same time and both units use the same time base ( share_clk), the outputs track very closely. if the circuit is in a polyphase configuration, all timing parameters must be the same. 4676fb for more information www.linear.com/LTM4676 ltm 4676
49 dac voltage error (not to scale) time delay of many seconds digital servo mode enabled final output voltage reached ton_max_fault_limit n ton_rise n time 4676 f03 ton_dela y n v outn run n vout_uv_fault_limit n figure 3. timing controlled v out rise a pplica t ions i n f or m a t ion coincident rail tracking can be achieved by setting two outputs to have the same turn-on/off slew rates, identical turn-on delays, and appropriately chosen turn-off delays: vout _command rail1 ton_rise rail1 = vout _command rail2 ton_rise rail2 and vout _command rail1 toff _fall rail1 = vout _command rail2 toff _fall rail2 and ton_delay rail1 = ton_delay rail2 and ( if vout_command rail2 vout_command rail1 ) toff _delay rail1 = toff _delay rail2 + 1C vout _command rail1 vout _command rail2 ? ? ? ? ? ? ? toff _fall rail2 or else ( vout _ command rail 2 < vout _ command rail 1 ) toff _delay rail2 = toff _delay rail1 + 1C vout _command rail2 vout _command rail1 ? ? ? ? ? ? ? toff _fall rail1 the described method of start- up sequencing is time based. for concatenated events it is possible to control the run pin based on the gpio n pin of a different controller (see figure? 2). the gpio n pin can be configured to release when the output voltage of the converter is greater than the vout_uv_fault_limit n . it is recommended to use the unfiltered v out uv fault limit because there is little appreciable time delay between the converter crossing the uv threshold and the gpio n pin releasing. the unfiltered output can be enabled by the mfr_ gpio_ propagate n [12] setting. (refer to the mfr section of the pmbus commands in the ltc3880 data sheet). the unfiltered signal may have some glitching as the v out signal transitions through the comparator threshold. a small digital filter of 250s internally deglitches the gpio n pins. if the ton_rise time is greater than 100 ms, the deglitch filter should be complimented with an externally applied capacitor between gpio n and groundto further filter the waveform. the rc time-constant of the filter should be set sufficiently fast to assure no appreciable delay is incurred . for most ap- plications, a value of 300 s to 500 s will provide sufficient filtering without significantly delaying the trigger event. d igit al s er vo m ode for maximum accuracy in the regulated output voltage, enable the digital servo loop by asserting bit 6 of the mfr_pwm_mode n command. in digital servo mode, the LTM4676 adjusts the regulated output voltage based on the adc voltage reading. every 100 ms the digital servo loop steps the lsb of the dac (nominally 1.375mv or 0.6875 mv depending on the voltage range bit, mfr_pwm_config[6- n ]) until the output is at the correct adc reading. at power-up this mode engages after ton_max_fault_limit n unless the limit is set to ?0 ( infinite). if the ton_max_fault_limit n is set to 0 ( infinite), the servo begins after ton_rise n is complete and v outn has exceeded vout_ uv_ fault_ limit n and iout_oc n is not present. this same point in time is when the output changes from discontinuous to the mode commanded by mfr_pwm_mode n [1:0]. refer to figure 3 for details on the v outn waveform under time based sequencing. 4676fb for more information www.linear.com/LTM4676 ltm 4676
50 a pplica t ions i n f or m a t ion if the ton_max_fault_limit n is set to a value greater than 0 and the ton_max_fault_response n is set to ignore (0x00), the servo begins: 1. after the ton_rise n sequence is complete 2. after the ton_max_fault_limit n time is reached; and 3. after the vout_uv_fault_limit n has been exceed or the iout_oc_fault_limit n is no longer active. if the ton_max_fault_limit n is set to a value greater than 0 and the ton_max_fault_response n is not set to ignore (0x00), the servo begins: 1. after the ton_rise n sequence is complete; 2. after the ton_max_fault_limit n time has expired and both vout_uv_fault n and iout_oc_fault n are not present. the maximum rise time is limited to 1.3 seconds. in a polyphase configuration it is recommended only one of the control loops have the digital servo mode enabled. this will assure the various loops do not work against each other due to slight differences in the reference circuits. s of t o ff (s equenced o ff ) in addition to a controlled start-up, the LTM4676 also supports controlled turn- off. the toff_ delay n and toff_fall n functions are shown in figure 4. toff_fall n is processed when the run n pin goes low or if the module is commanded off. if the module faults off or gpio n is pulled low externally and the module is programmed to respond to this (mfr_gpio_response n = 0 xc0), the output three - states ( becomes high impedance) rather than exhibiting a controlled ramp. the output then decays as a function of the load. the output voltage operates as shown in figure 4 so long as the part is in forced continuous mode and the toff_fall n time is sufficiently slow that the power stage can achieve the desired slope. the toff_fall n time can only be met if the power stage and controller can sink sufficient current to assure the output is at zero volts by the end of the fall time interval. if the toff_fall n time is set shorter than the time required to discharge the load capacitance, the output will not reach the desired zero volt state. at the end of toff_fall n , the controller ceases to sink current and v outn decays at the natural rate determined by the load impedance. if the controller is in discontinuous mode , the controller does not pull negative current and the output becomes pulled low by the load, not the power stage. the maximum fail time is limited to 1.3 seconds. the number of steps in the ramp is equal to toff_fall/0.1ms.therefore, the shorter the toff_fall n setting, the more jagged the toff_fall n ramp appears. u nder voltage l ockout the LTM4676 is initialized by an internal threshold- based uvlo where sv in must be approximately 4 v and intv cc , v dd33 , v dd25 must be within approximately 20% of the regulated values. in addition, v dd33 must be within approximately 7% of the targeted value before the LTM4676 releases its run n pins. after the part has initialized, an additional comparator monitors sv in . the vin_on threshold must be exceeded before the power sequencing can begin. when sv in drops below the vin_ off threshold, the LTM4676 pulls its run n pins low and sv in must increase above the vin_on threshold before the controller will restart. the normal start-up sequence will be allowed after the vin_on threshold is crossed. it is possible to program the contents of the nvm in the application if the v dd33 supply is externally driven. this activates the digital portion of the LTM4676 without engaging the high voltage sections. pmbus communications are valid in this supply configura - tion. if sv in has not been applied to the LTM4676 , figure 4. toff_delay n and toff_fall n toff_fall n toff_delay n time 4676 f04 v outn run n 4676fb for more information www.linear.com/LTM4676 ltm 4676
51 a pplica t ions i n f or m a t ion mfr_common[3] will be asserted low, indicating that nvm has not initialized. if this condition is detected, the part will only respond to addresses 0 x5a and 0 x5b. to initialize the part issue the following set of commands: global address 0 x5b command 0 xbd data 0 x2b followed by global address 0 x5b command 0 xbd and data 0xc4. the part will now respond to the correct address. configure the part as desired then issue a store_user_all. when sv in is applied a mfr_reset command must be issued to allow the pwm to be enabled and valid adc conver- sions to be read. f ault c onditions the LTM4676 gpio n pins are configurable to indicate a variety of faults including ov/uv, oc, ot, timing faults, peak overcurrent faults. in addition the gpio n pins can be pulled low by external sources to indicate to the LTM4676 the presence of a fault in some other portion of the system. the fault response is configurable and allow the following options: n ignore n shut down immediatelylatch off n shut down immediatelyretry indefinitely at the time interval specified in mfr_retry_dela y n refer to the pmbus section of the ltc3880 data sheet and the pmbus specification for more details. the ov response is automatic and rapid. if an ov is de - tected, mt n is turned off and bg n is turned on, until the ov condition clears. fault logging is available on the LTM4676. the fault log - ging is configurable to automatically store data when a fault occurs that causes the unit to fault off. the header portion of the fault logging table contains peak values. it is possible to read these values at any time. this data will be useful while troubleshooting the fault. if the LTM4676 internal temperature is in excess of 85c or below 0 c, the write into the nvm is not recommended. the data will still be held in ram, unless the 3.3 v supply uvlo threshold is reached. if the die temperature exceeds 130c all nvm communication is disabled until the die temperature drops below 125c. o pen -d rain p ins the LTM4676 has the following open-drain pins: 3.3 v pins 1. gpio n 2. sync 3. share_clk 5v pins ( compatible with 3.3 v digital logic thresholds) 1. run n 2. alert 3. scl 4. sda all the above pins have on-chip pull-down transistors that can sink 3 ma at 0.4 v. the low threshold on the pins is 1.4 v; thus, plenty of margin on the digital signals with 3 ma of current. for 3.3 v pins, 3 ma of current is a 1.1 k resistor. unless there are transient speed issues associated with the rc time constant of the resistor pull- up and parasitic capacitance to ground, a 10 k resistor or larger is generally recommended. for high speed signals such as the sda, scl and sync, a lower value resistor may be required. the rc time con - stant should be set to 1/3 to 1/5 the required rise time to avoid timing issues. for a 100 pf load and a 400khz pmbus communication rate, the rise time must be less than 300 ns. the resistor pull-up on the sda and scl pins with the time constant set to 1/3 the rise time: r pullup = t rise 3 ? 100pf = 1k be careful to minimize parasitic capacitance on the sda and scl pins to avoid communication problems. to estimate the loading capacitance, monitor the signal in question and measure how long it takes for the desired signal to reach approximately 63% of the output value. this is one time constant. the sync pin has an on-chip pull-down transistor with the output held low for nominally 500 ns. if the internal oscillator is set for 500 khz and the load is 100 pf and a 4676fb for more information www.linear.com/LTM4676 ltm 4676
52 a pplica t ions i n f or m a t ion 3x time constant is required, the resistor calculation is as follows: r pullup = 2s C 500ns 3 ? 100pf = 5k the closest 1% resistor is 4.99k. if timing errors are occurring or if the sync frequency is not as fast as desired, monitor the waveform and determine if the rc time constant is too long for the application. if possible reduce the parasitic capacitance. if not reduce the pull up resistor sufficiently to assure proper timing. p hase -l ocked l oop and f requency s ynchroni z a tion the LTM4676 has a phase-locked loop ( pll) comprised of an internal voltage-controlled oscillator ( vco) and a phase detector. the pll is locked to the falling edge of the sync pin. the phase relationship between channel 0, channel 1 and the falling edge of sync is controlled by the lower 3 bits of the mfr_pwm_config command. for polyphase applications, it is recommended all the phases be spaced evenly. thus for a 2- phase system the signals should be 180 out of phase and a 4- phase system should be spaced 90. the phase detector is an edge-sensitive digital type that provides a known phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complemen - tary current sources that charge or discharge the internal filter network. the pll lock range is guaranteed between 225khz and 1.1mhz. the pll has a lock detection circuit. if the pll should lose lock during operation, bit 4 of the status _ mfr _ specific command is asserted and the alert pin is pulled low. the fault can be cleared by writing a 1 to the bit. if the user does not wish to see the pll_fault, even if a synchronization clock is not available at power up, bit 3 of the mfr_config_all command must be asserted. if the sync signal is not clocking in the application, the pll runs at the lowest free running frequency of the vco. this will be well below the intended pwm frequency of the application and may cause undesirable operation of the converter. if the pwm (swn ) signal appears to be running at too high a frequency, monitor the sync pin. extra transitions on the falling edge will result in the pll trying to lock on to noise instead of the intended signal. review routing of digital control signals and minimize crosstalk to the sync signal to avoid this problem. multiple LTM4676s are required to share the sync pin in polyphase configurations; for other configurations, it is optional. if the sync pin is shared between LTM4676s, only one LTM4676 can be programmed with a frequency output. all the other LTM4676s must be configured for external clock (frequency_switch = 0x0000, and/or see table 4). rconfig p in -s traps (e xternal r esistor c onfiguration p ins ) the LTM4676 default nvm is programmed to respect the rconfig pins. if a user wishes the output voltage, pwm frequency and phasing and the address to be set without programming the part or purchasing specially programmed parts, the rconfig pins can be used to establish these parametersprovided mfr_ config_ all[6] = 0 b . the rconfig pins only require a resistor terminating to sgnd of the LTM4676. the rconfig pins are only monitored at initial power up and during a reset (mfr_reset) so modifying their values perhaps using a dac after the part is powered will have no effect. to assure proper operation, the value of rconfig resistors applied to the LTM4676 pin-strapping pins must not deviate more than 3% away from the target nominal values indicated in lookup tables?2 to 5, over the lifetime of the product. thin film , 1% tolerance ( or better ), 50ppm/c-t.c.r. rated ( or better) resistors from vendors such as koa speer, panasonic, vishay and yageo are good candidates. noisy clock signals should not be routed near these pins. v ol tage s election when an output voltage is set using the rconfig pins on voutn _cfg and vtrimn_cfg (mfr_config_all[6] = 0 b ), the following parameters are set as a percentage of the output voltage: 4676fb for more information www.linear.com/LTM4676 ltm 4676
53 figure 5. lt c controller connection suitable for programming nvm of up to 16 LTM4676s when v in power is absent, 0c < t j 85c a pplica t ions i n f or m a t ion ? vout_ov_fault_limit +10% ? vout_ov_w arn +7.5% ? vout_max +7.5% ? vout_margin_hi +5% ? power_good_on C7% ? power_good_off C8% ? vout_margin_lo C5% ? vout_uv_w arn C6.5% ? vout_uv_fault_limit C7% c onnecting the usb to the i 2 c/smbus/pmbus c ontroller to the LTM4676 i n s ystem the lt c usb to i 2 c/smbus/pmbus controller can be interfaced to the LTM4676 on the users board for pro- gramming, telemetr y and system debug. the controller, when used in conjunction with ltpowerplay, provides a powerful way to debug an entire power system. faults are quickly diagnosed using telemetry, fault status registers and the fault log. the final configuration can be quickly developed and stored to the LTM4676 eeprom. figures 5 and 6 illustrate the application schematics for powering, programming and communicating with one or more LTM4676 s via the ltc i 2 c/ smbus/ pmbus controller regardless of whether or not system power is present. if system power is not present the dongle will power the LTM4676 through the v dd33 supply pin. to initialize the part when sv in is not applied and the v dd33 pin is powered use global address 0 x5b command 0 xbd data 0x2b followed by address 0 x5b command 0 xbd data 0xc4. the part can now be communicated with, and the project file updated. to write the updated project file to the nvm issue a store_user_all command. when sv in is applied, a mfr_reset must be issued to allow the pwm to be enabled and valid adcs to be read. because of the controllers limited current sourcing capability, only the LTM4676s, their associated pull-up resistors and the i 2 c pull-up resistors should be powered from the ored 3.3v/3.4v supply. in addition, any device sharing the i 2 c bus connections with the LTM4676 must not have body diodes between the sda/scl pins and their respective v dd node because this will interfere with bus communication in the absence of system power. in figure? 5, the dongle will not bias the LTM4676s when sv in v in v dd33 v dd25 sda vgs max on the tp0101k is 8v. if v in > 16v, change the resistor divider on the pfet gate alternate pfets/packages: sot-723: on semi ntk3139pt1g, rohm rzm002p02t2l sot-523: diodes inc. dmg1013t-7 sot-563: diodes inc. dmp2104v-7 on semi ntzs3151pt1g sot-323: diodes inc. dmg1013uw-7 on semi nts2101pt1g vishay si1303dl-t1-e3 4676 f05 10k 100k tp0101k sot-23 see tables 9-13 for connector and pinout options isolated 3.4v (usually needed) scl sda tp0101k sot-23 100k to ltc dc2086 digital power programming adapter (requires ltc dc1613 usb to i 2 c/smbus/ pmbus controller) module programming and communication interface header scl wp sgnd LTM4676 sv in v dd33 sda scl wp sgnd LTM4676 ? ? ? ? ? ? 10k v dd25 4676fb for more information www.linear.com/LTM4676 ltm 4676
54 a pplica t ions i n f or m a t ion sv in is present. it is recommended the run n pins be held low to avoid providing power to the load until the part is fully configured. the lt c controller/adapter i 2 c connections are opto- isolated from the pc usb. the 3.3v /3/4 v from the controller/adapter and the LTM4676 v dd33 pin must be driven to each LTM4676 with a separate pfet or diode, according to figures 5 and 6. only when sv in is not ap- plied is it permissible for the v dd33 pins to be electrically in parallel because the intv cc ldo is off. the dc1613s 3.3v current limit is 100 ma but typical v dd33 currents are under 15 ma. the v dd33 does back drive the intv cc pin. normally this is not an issue if sv in is open. the dc2086 is capable of delivering 3.4v at 2a. using a 4- pin header in figure 5 or 6 maximizes flexibility to alter the LTM4676s nvm contents at any stage of the users product development and production cycles. if the LTM4676s nvm is pre-programmed, i.e., contains its finalized configuration, prior to being soldered to the users pcb/motherboardor, if other means have been provided for altering the LTM4676's nvm contents in the users systemthen the 3.3 v/3.4v pin on the header is not needed, and a 3- pin header is sufficient to establish gui communications. the LTM4676 can be purchased with customized nvm contents; consult factory for details. alternatively, the nvm contents of the LTM4676 can be configured in a mass production environment by design - ing for it in ict ( in-circuit test), or by providing a means of applying sv in while holding the LTM4676s run pins low. communication to the module must be made possible via the scl and sda pins/nets in all nvm programming scenarios. recommended headers are found in tables 9 and 10. ltpowerplay: a n i nteractive gui for d igit al p ower s ystem m anagement ltpowerplay is a powerful windows-based development environment that supports linear technology digital power ics including the LTM4676. the software supports a variety of different tasks. ltpowerplay can be used to evaluate linear technology ics by connecting to a demo board or the user application. ltpowerplay can also be used in an offline mode ( with no hardware present) in order to build multiple ic configuration files that can be saved and reloaded at a later time. ltpowerplay provides unprecedented diagnostic and debug features. it becomes sv in v in v dd33 v dd25 sda d1, d2: nxp pmeg2005ael or pmeg2005aeld. diode selection is not arbitrary. use v f < 210mv at i f = 20ma 4676 f06 10k see tables 9-13 for connector and pinout options isolated 3.4v (usually needed) scl d1 sod882 sda module programming and communication interface header to ltc dc2086 digital power programming adapter (requires ltc dc1613 usb to i 2 c/smbus/ pmbus controller) scl wp sgnd LTM4676 sv in v dd33 sda scl wp sgnd LTM4676 ? ? ? ? ? ? 10k v dd25 d2 sod882 figure 6. lt c controller connection suitable for programming nvm of up to 16 LTM4676s when v in power is absent, t a > 20c and t j < 85c 4676fb for more information www.linear.com/LTM4676 ltm 4676
55 a pplica t ions i n f or m a t ion table 9. 4-pin headers, 2mm pin-to-pin spacing, gold flash or plating, compatible with dc2086 cables mounting style insertion angle interface style vendor part number pinout style (see table 11) surface mount vertical shrouded and keyed header hirose df3dz-4p-2v(51) df3dz-4p-2v(50) df3z-4p-2v(50) t ype a non shrouded, non-keyed header 3m 951104-2530-ar-pr type a and b supported. reversible/not keyed right angle shrouded and keyed header hirose df3dz-4p-2h(51) df3dz-4p-2h(50) t ype a non shrouded. cable-to-header/pcb mechanics y ield keying effect fci 10112684-g03-04ulf type b. keying achieved by pcb surface through-hole vertical shrouded and keyed header hirose df3-4p-2dsa(01) type a non shrouded, non-keyed header harwin m22-2010405 type a and b supported. reversible/not keyed samtec tmm-104-01-ls sullins nrpn041paen-rc right angle shrouded and keyed header hirose df3-4p-2ds(01) type a non shrouded. cable-to-header/pcb mechanics yield keying effect norcomp 27630402rp2 type b. keying achieved by intentional pcb interference harwin m22-2030405 samtec tmm-104-01-l-s-ra table 10. 3-pin headers, 2mm pin-to-pin spacing, gold flash or plating, compatible with dc2086 cables mounting style insertion angle interface style vendor part number pinout style (see table 12) surface mount vertical shrouded and keyed header hirose df3dz-3p-2v(51) df3dz-3p-2v(50) df3z-3p-2v(50) t ype a non shrouded, non-keyed header 3m 951103-2530-ar-pr type a and b supported. reversible/not keyed right angle shrouded and keyed header hirose df3dz-3p-2h(51) df3dz-3p-2h(50) t ype a non shrouded. cable-to-header/pcb mechanics yield keying effect fci 10112684-g03-03lf type b. keying achieved by pcb surface through-hole vertical shrouded and keyed header hirose df3-3p-2dsa(01) type a non shrouded, non-keyed header harwin m22-2010305 type a and b supported. reversible/not keyed samtec tmm-103-01-ls sullins nrpn031paen-rc right angle shrouded and keyed header hirose df3-3p-2ds(01) type a non shrouded. cable-to-header/pcb mechanics yield keying effect norcomp 27630302rp2 type b. keying achieved by intentional pcb interference harwin m22-2030305 samtec tmm-103-01-l-s-ra table 11. recommended 4-pin header pinout (pin numbering scheme adheres to hirose conventions). interfaces to dc2086 cables pin number pinout style a (see table 9) pinout st yle b (see table 9) 1 sda isolated 3.3v/3.4v 2 gnd scl 3 scl gnd 4 isolated 3.3v/3.4v sda table 12. recommended 3-pin header pinout (pin numbering scheme adheres to hirose conventions). interfaces to dc2086 cables pin number pinout style a (see table 10) pinout style b (see table 10) 1 sda scl 2 gnd gnd 3 scl sda 4676fb for more information www.linear.com/LTM4676 ltm 4676
56 a pplica t ions i n f or m a t ion a valuable diagnostic tool during board bring-up to pro- gram or tweak the power system or to diagnose power issues when bringing up rails. ltpowerplay utilizes linear technology s usb- to -i 2 c/ smbus/ pmbus controller to communication with one of the many potential targets including the dc 1811 ( single LTM4676) or dc 1989 ( dual, triple, quad LTM4676) demo boards, or a customer target system. the software also provides an automatic update feature to keep the revisions current with the latest set of device drivers and documentation. a great deal of context table 13. 4-pin male-to-male shrouded and keyed adapter (optional. eases creation of adapter cables, if deviating from recommended connectors/connector pinouts). interfaces to dc2086 cables vendor part number website hirose df3-4ep-2a www.hirose.com, www.hirose.co.jp figure 7 sensitive help is available with ltpowerplay along with several tutorial demos. complete information is available at http://www.linear.com/ltpowerplay pm bus c ommunica tion and c ommand p rocessing the LTM4676 has one deep buffer to hold the last data written for each supported command prior to processing as shown in figure 8; write command data processing. when the part receives a new command from the bus, it copies the data into the write command data buffer, indicates to the internal processor that this command data needs to be fetched, and converts the command to its internal format so that it can be executed. 4676fb for more information www.linear.com/LTM4676 ltm 4676
57 a pplica t ions i n f or m a t ion tw o distinct parallel blocks manage command buffering and command processing ( fetch, convert, and execute) to ensure the last data written to any command is never lost. command data buffering handles incoming pm - bus writes by storing the command data to the write command data buffer and marking these commands for future processing. the internal processor runs in parallel and handles the sometimes slower task of fetching, con - verting and executing commands marked for processing. some computationally intensive commands ( e.g., timing parameters, temperatures, voltages and currents) have internal processor execution times that may be long relative to pmbus timing. if the part is busy processing a command, and new command(s) arrive, execution may be delayed or processed in a different order than received. the part indicates when internal calculations are in process via bit?5 of mfr_common ( calculations not pending). when the part is busy calculating, bit 5 is cleared. when this bit is set, the part is ready for another command. an example polling loop is provided in figure 8 which ensures that commands are processed in order while simplifying error handling routines. when the part receives a new command while it is busy, it will communicate this condition using standard pmbus protocol. depending on part configuration it may either nack the command or return all ones (0 xff) for reads. it may also generate a busy fault and alert notification, or stretch the scl clock low. for more information refer to pmbus specification v1.1, part ii, section 10.8.7 and smbus v2.0 section 4.3.3. clock stretching can be enabled by asserting bit 1 of mfr_config_all. clock stretching will only occur if enabled and the bus communication speed exceeds 100khz. pmbus busy protocols are well accepted standards, but can make writing system level software somewhat com - plex. the part provides three hand shaking status bits which reduce complexity while enabling robust system level communication. the three hand shaking status bits are in the mfr_ common register . when the part is busy executing an internal operation, it will clear bit 6 of mfr_common (chip not busy). when the part is busy specifically because it is in a transitional vout state ( margining hi/lo, power off/on, moving to a new output voltage set point, etc.) it will clear bit 4 of mfr_common ( output not in transition). when internal calculations are in process, the part will clear bit?5 of mfr_common (calculations not pending ). these three status bits can be polled with a pmbus read byte of the mfr_common register until all three bits are set. a command immediately following the status bits being set will be accepted without nacking or generating a busy fault/ alert notification. the part can nack commands for other reasons, however, as required by the pmbus spec ( for instance, an invalid command or data). an example of a robust command write algorithm for the vout_ command n register is provided in figure 9. decoder cmd internal processor write command data buffer page cmds 0x00 0x21 0xfd 4676 f08 x1 ? ? ? ? ? ? mfr_reset vout_command s calculations pending pmbus write r fetch, convert data and execute data mux figure 8. write command data processing figure 9. example of a command write of vout_command // wait until bits 6, 5, and 4 of mfr_common are all set do { mfrcommonvalue = pmbus_read_byte(0xef); partready = (mfrcommonvalue & 0x68) == 0x68; }while(!partready) // now the part is ready to receive the next command pmbus_write_word(0x21, 0x2000); //write vout_command to 2v it is recommended that all command writes ( write byte, write word, etc.) be preceded with a polling loop to avoid the extra complexity of dealing with busy behavior and unwanted alert notification. a simple way to achieve this is by creating safe_write_byte() and safe_write_ word() subroutines. the above polling mechanism allows ones software to remain clean and simple while robustly communicating with the part. for a detailed discussion of these topics and other special cases please refer to the application note section located at www.linear.com/ designtools/app_notes. 4676fb for more information www.linear.com/LTM4676 ltm 4676
58 a pplica t ions i n f or m a t ion when communicating using bus speeds at or below 100khz, the polling mechanism shown here provides a simple solution that ensures robust communication without clock stretching. at bus speeds in excess of 100 khz, it is strongly recommended that the part be configured to en - able clock stretching. this requires a pmbus master that supports clock stretching. system software that detects and properly recovers from the standard pmbus nack/ busy faults as described in the pmbus specification v1.1, part ii, section 10.8.7 is required to communicate above 100khz without clock stretching. clock stretching will not extend the pmbus speed beyond the specified 400khz. t hermal c onsidera tions and o utput c urrent d erating the thermal resistances reported in the pin configuration section of this data sheet are consistent with those pa- rameters defined by jesd51-12 and are intended for use with finite element analysis ( fea) software modeling tools that leverage the outcome of thermal modeling, simula- tion, and correlation to hardware evaluation performed on a module package mounted to a hardware test board defined by jesd 51-9 ( test boards for area array surface mount package thermal measurements). the motivation for providing these thermal coefficients is found in jesd 51-12 ( guidelines for reporting and using electronic package thermal information). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the module regulators thermal performance in their application at various electrical and environmental operating conditions to compliment any fea activities. without fea software, the thermal resistances reported in the pin configuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided later in this data sheet can be used in a manner that yields insight and guidance pertaining to ones application-usage, and can be adapted to correlate thermal performance to ones own application. the pin configuration section gives four thermal coeffi - cients explicitly defined in jesd 51-12; these coefficients are quoted or paraphrased below: 1 ja , the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo - sure. this environment is sometimes referred to as still air although natural convection causes the air to move . this value is determined with the part mounted to a jesd 51-9 defined test board, which does not reflect an actual application or viable operating condition. 2 jcbottom , the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. in the typical module regulator, the bulk of the heat flows out the bottom of the pack - age, but there is always heat flow out into the ambient environment. as a result, this thermal resistance value may be useful for comparing packages but the test conditions dont generally match the users application. 3 jctop , the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part . as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. 4 jb , the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resis- tance where almost all of the heat flows through the bottom of the module regulator and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured a specified distance from the package, using a two sided, two layer board. this board is described in jesd 51-9. 4676fb for more information www.linear.com/LTM4676 ltm 4676
59 a pplica t ions i n f or m a t ion a graphical representation of the aforementioned thermal resistances is given in figure 10; blue resistances are contained within the module regulator, whereas green resistances are external to the module package. as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by jesd 51-12 or provided in the pin configuration section replicates or conveys normal operating conditions of a module regulator. for example, in normal board-mounted applications, never does 100% of the devices total power loss (heat) thermally conduct exclusively through the top or exclusively through bot - tom of the module packageas the standard defines for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the packagegranted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. within the LTM4676, be aware there are multiple power devices and components dissipating power, with a con - sequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. to reconcile this complication without sacrificing modeling simplicity but also, not ignoring practical realities an approach has been taken using fea software modeling along with laboratory testing in a controlled-environment chamber to reason- ably define and correlate the thermal resistance values supplied in this data sheet : (1) initially, fea software is used to accurately build the mechanical geometry of the LTM4676 and the specified pcb with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined jedec environment consistent with jsed 51-9 and jesd 51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the jedec-defined thermal resistance values ; (3) the model and fea software is used to evaluate the LTM4676 with heat sink and airflow ; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled envi - ronment chamber while operating the device at the same power loss as that which was simulated. the outcome of this process and due diligence yields the set of derating curves provided in later sections of this data sheet, along with well- correlated jesd51-12-defined values provided in the pin configuration section of this data sheet. t he 1 v , 1.8 v and 3.3 v power loss curves in figures 11 , 12 and 13 respectively can be used in coordination with the load current derating curves in figures 14 to 31 for calculating an approximate ja thermal resistance for the ltm 4676 with various heat sinking and air flow conditions . these thermal resistances represent demonstrated performance of the ltm 4676 on dc 1543 hardware ; a 4- layer fr 4 pcb measuring 99 mm 113 mm 1.6 mm using outer and inner copper weights of 2 oz and 1 oz , respectively . the power loss curves are taken at room temperature , and are increased with multiplicative factors with ambient temperature . these approximate factors are listed in table 14. 4676 f10 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient resistance (jesd 51-9 defined board) case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance figure 10. graphical representation of jesd51-12 thermal coefficients 4676fb for more information www.linear.com/LTM4676 ltm 4676
60 a pplica t ions i n f or m a t ion ( compute the factor by interpolation , for intermediate temperatures .) the derating curves are plotted with the ltm 4676 s paralleled outputs initially sourcing up to 26 a and the ambient temperature at 30 c. the output voltages are 1 v , 1.8 v and 3.3 v. these are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance . thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling ana lysis. the junction temperatures are monitored w hile a mbient temperature is increased with and without air flow , and with and without a heat sink attached with thermally conductive adhesive tape . the bga heat sinks evaluated in table 18 ( and attached to the ltm 4676 with thermally conductive adhesive tape listed in table ?19) yield very comparable performance in laminar airflow despite being visibly different in construction and form factor . the power loss increase with ambient temperature change is factored into the derating curves . the junctions are maintained at 120 c maximum while lowering output current or power while increasing ambient temperature . the decreased output current decreases the internal module loss as ambient temperature is increased . the monitored junction temperature of 120 c minus the ambient operating temperature specifies how much m odule t emperature rise can be allowed . as an example in figure 15 , the load current is derated to ~19 a at ~80 c ambient with 400 lfm airflow and no heat sink and the room temperature (25 c) power loss for this 12 v in to 1 v out at 19 a out condition is ~4 w. a 4.8 w loss is calculated by multiplying the ~4 w room temperature loss from the 12 v in to 1 v out power loss curve at 19 a ( figure 11 ), with the 1.2 multiplying factor at 80 c ambient ( from table?14). if the 80 c ambient temperature is subtracted from the 120 c junction temperature , then the difference of 40 c divided by 4.8 w yields a thermal resistance , ja , of 8.3 c/w in good agreement with table 15. tables ?15, 16 and 17 provide equivalent thermal resistances for 1 v , 1.8 v and 3.3 v outputs with and without air flow and heat sinking . the derived thermal resistances in tables 15, 16 and 17 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient , thus maximum junction temperature . room temperature power loss can be derived from the efficiency curves in the typical performance characteristics section and adjusted with ambient temperature multiplicative factors from table 14. table 14. power loss multiplicative factors vs ambient temperature ambient temperature power loss multiplicative factor up to 40c 1.00 50c 1.05 60c 1.10 70c 1.15 80c 1.20 90c 1.25 100c 1.30 110c 1.35 120c 1.40 4676fb for more information www.linear.com/LTM4676 ltm 4676
61 a pplica t ions i n f or m a t ion table 15. 1.0v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 14, 15, 16 5, 12, 24 figure 11 0 none 10.6 figures 14, 15, 16 5, 12, 24 figure 11 200 none 9.5 figures 14, 15, 16 5, 12, 24 figure 11 400 none 8.5 figures 17, 18, 19 5, 12, 24 figure 11 0 bga heat sink 9.8 figures 17, 18, 19 5, 12, 24 figure 11 200 bga heat sink 8.2 figures 17, 18, 19 5, 12, 24 figure 11 400 bga heat sink 7.1 table 16. 1.8v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 20, 21, 22 5, 12, 24 figure 12 0 none 10.7 figures 20, 21, 22 5, 12, 24 figure 12 200 none 9.4 figures 20, 21, 22 5, 12, 24 figure 12 400 none 8.4 figures 23, 24, 25 5, 12, 24 figure 12 0 bga heat sink 9.9 figures 23, 24, 25 5, 12, 24 figure 12 200 bga heat sink 8.3 figures 23, 24, 25 5, 12, 24 figure 12 400 bga heat sink 7.1 table 17. 3.3v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figure 26, 27, 28 5, 12, 24 figure 13 0 none 10.6 figure 26, 27, 28 5, 12, 24 figure 13 200 none 9.3 figure 26, 27, 28 5, 12, 24 figure 13 400 none 8.4 figure 29, 30, 31 5, 12, 24 figure 13 0 bga heat sink 10.0 figure 29, 30, 31 5, 12, 24 figure 13 200 bga heat sink 8.4 figure 29, 30, 31 5, 12, 24 figure 13 400 bga heat sink 7.3 table 18. heat sink manufacturer (thermally conductive adhesive tape pre-attached) heat sink manufacturer part number website aavid thermalloy 375424b00034g www.aavid.com cool innovations 4-050503pt 411 www.coolinnovations.com wakefield engineering lt n 20069 www.wakefield.com table 19. thermally conductive adhesive tape vendor thermally conductive adhesive tape manufacturer part number website chomerics t411 www.chomerics.com 4676fb for more information www.linear.com/LTM4676 ltm 4676
62 a pplica t ions i n f or m a t ion v outn (v) v inn (v) ref. circuit* c outhn (ceramic output cap) c outln (bulk output cap) connect comp n a to comp n b ? (internal loop comp) r thn (ext loop comp) (k) c thn (ext loop comp) (nf) f sw (khz) f swphcfg pin- strap, resistor to sgnd (table 4) (k) v outn cfg pin- strap resistor to sgnd (table 2) (k) v trimn cfg pin- strap, resistor to sgnd (table 3) (k) trans- ient droop (0a to 6.5a) (mv) pk-pk devi- ation (0a to 6.5a to 0a) (mv) recov- ery time (s) 0.9 5 test ckt. 2 100f 7 none yes , cf. fig. 44 n/a n/a 350 22.6 1.65 none 42 79 45 0.9 5 test ckt. 2 100f 3 330f no. use r th , c th 4.12 2.2 350 22.6 1.65 none 91 162 40 0.9 12 test ckt. 1 100f 7 none yes , cf. fig. 44 n/a n/a 350 22.6 1.65 none 42 79 45 0.9 12 test ckt. 1 100f 3 330f no. use r th , c th 4.12 2.2 350 22.6 1.65 none 91 162 40 0.9 24 test ckt. 1 100f 7 none yes , cf. fig. 44 n/a n/a 250 32.4 1.65 none 45 85 45 0.9 24 test ckt. 1 100f 3 330f no. use r th , c th 4.12 2.2 350 22.6 1.65 none 94 165 40 1 5 test ckt. 2 100f 7 none ye s , cf. fig. 44 n/a n/a 350 22.6 2.43 0 44 85 45 1 5 test ckt. 2 100f 3 330f no. use r th , c th 4.22 2.2 350 22.6 2.43 0 90 160 40 1 12 test ckt. 1 100f 7 none yes , cf. fig. 44 n/a n/a 350 22.6 2.43 0 44 85 45 1 12 test ckt. 1 100f 3 330f no. use r th , c th 4.22 2.2 350 22.6 2.43 0 90 160 40 1 24 test ckt. 1 100f 7 none yes , cf. fig. 44 n/a n/a 250 32.4 2.43 0 47 90 45 1 24 test ckt. 1 100f 3 330f no. use r th , c th 4.22 2.2 350 22.6 2.43 0 93 164 40 1.2 5 test ckt. 2 100f 7 none yes , cf. fig. 44 n/a n/a 350 22.6 3.24 0 45 85 45 1.2 5 test ckt. 2 100f 3 330f no. use r th , c th 4.42 2.2 350 22.6 3.24 0 89 149 40 1.2 12 test ckt. 1 100f 7 none yes , cf. fig. 44 n/a n/a 350 22.6 3.24 0 45 85 45 1.2 12 test ckt. 1 100f 3 330f no. use r th , c th 4.42 2.2 350 22.6 3.24 0 89 149 40 1.2 24 test ckt. 1 100f 7 none yes , cf. fig. 44 n/a n/a 350 22.6 3.24 0 48 81 45 1.2 24 test ckt. 1 100f 3 330f no. use r th , c th 4.42 2.2 350 22.6 3.24 0 92 154 40 1.5 5 test ckt. 2 100f 7 none yes , cf. fig. 44 n/a n/a 350 22.6 4.22 none 45 85 45 1.5 5 test ckt. 2 100f 3 330 f no. use r th , c th 4.75 2.2 350 22.6 4.22 none 89 149 40 1.5 12 test ckt. 1 100f 7 none yes , cf. fig. 44 n/a n/a 350 22.6 4.22 none 45 85 45 1.5 12 test ckt. 1 100f 3 330f no. use r th , c th 4.75 2.2 350 22.6 4.22 none 89 149 40 1.5 24 test ckt. 1 100f 7 none yes , cf. fig. 44 n/a n/a 425 18.0 4.22 none 48 91 45 1.5 24 test ckt. 1 100f 3 330f no. use r th , c th 4.75 2.2 350 22.6 4.22 none 93 156 40 1.8 5 test ckt. 2 100f 7 none yes , cf. fig. 44 n/a n/a 425 18.0 6.34 0 45 85 45 1.8 5 test ckt. 2 100f 3 330f no. use r th , c th 4.99 2.2 500 none 6.34 0 88 144 40 1.8 12 test ckt. 1 100f 7 none yes , cf. fig. 44 n/a n/a 500 none 6.34 0 45 85 45 1.8 12 test ckt. 1 100f 3 330f no. use r th , c th 4.99 2.2 500 none 6.34 0 88 144 40 1.8 24 test ckt. 1 100f 7 none yes , cf. fig. 44 n/a n/a 500 none 6.34 0 48 92 45 1.8 24 test ckt. 1 100f 3 330f no. use r th , c th 4.99 2.2 500 none 6.34 0 94 158 40 table 20. LTM4676 channel output voltage response vs component matrix. 6.5a load-stepping at 6.5a/s. typical measured values c outh vendors part number c outl vendors part number avx 12106d107 mat 2a (100f, 6.3v, 1210 case size) sanyo poscap 6tpf330m9l (330f, 6.3v, 9m esr, d3l case size) murata grm32er60j107me20l (100f, 6.3v, 1210 case size) sanyo poscap 6tpd470m (470f, 6.3v, 10m esr, d4d case size) taiyo yuden jmk325bj107mm-t (100f, 6.3v, 1210 case size) sanyo poscap 2r5tpe470m9 (470f, 2.5v, 9m esr, d2e case size) tdk c3225x5r0j107mt (100f, 6.3v, 1210 case size) 4676fb for more information www.linear.com/LTM4676 ltm 4676
63 a pplica t ions i n f or m a t ion figure 11. 1v out power loss curve figure 12. 1.8v out power loss curve figure 13. 3.3v out power loss curve output current (a) 0 2 4 power loss (w) 4 6 4676 f11 2 0 6 8 10 12 14 16 18 20 22 24 26 8 24v in 5v in 3 5 1 7 12v in output current (a) 0 power loss (w) 6 8 10 18 4676 f12 4 2 5 7 9 3 1 0 4 8 12 22 2 20 6 10 14 16 24 26 24v in 5v in 12v in output current (a) 0 2 4 power loss (w) 8 12 4676 f13 4 0 6 8 10 12 14 16 18 20 22 24 26 14 24v in 5v in 6 10 2 12v in table 20. LTM4676 channel output voltage response vs component matrix. 6.5a load-stepping at 6.5a/s. typical measured values v outn (v) v inn (v) ref. circuit* c outhn (ceramic output cap) c outln (bulk output cap) connect comp n a to comp n b ? (internal loop comp) r thn (ext loop comp) (k) c thn (ext loop comp) (nf) f sw (khz) f swphcfg pin- strap, resistor to sgnd (table 4) (k) v outn cfg pin- strap resistor to sgnd (table 2) (k) v trimn cfg pin- strap, resistor to sgnd (table 3) (k) trans- ient droop (0a to 6.5a) (mv) pk-pk devi- ation (0a to 6.5a to 0a) (mv) recov- ery time (s) 2.5 5 test ckt. 2 100f 7 none yes , cf. fig. 44 n/a n/a 425 18.0 10.7 none 46 86 45 2.5 5 test ckt. 2 100f 3 330f no. use r th , c th 5.62 2.2 575 15.4 10.7 none 89 148 40 2.5 12 test ckt. 1 100f 7 none yes , cf. fig. 44 n/a n/a 575 15.4 10.7 none 46 86 45 2.5 12 test ckt. 1 100f 3 330f no. use r th , c th 5.62 2.2 575 15.4 10.7 none 90 150 40 2.5 24 test ckt. 1 100f 7 none yes , cf. fig. 44 n/a n/a 650 12.7 10.7 none 48 94 45 2.5 24 test ckt. 1 100f 3 330f no. use r th , c th 5.62 2.2 650 12.7 10.7 none 92 154 40 3.3 5 test ckt. 2 100f 5 none ye s , cf. fig. 44 n/a n/a 425 18.0 22.6 none 56 110 45 3.3 12 test ckt. 1 100f 5 none yes , cf. fig. 44 n/a n/a 650 12.7 22.6 none 60 112 45 3.3 24 test ckt. 1 100f 5 none yes , cf. fig. 44 n/a n/a 750 10.7 22.6 none 62 115 45 5** 12 test ckt. 1 100f 5 none yes , cf. fig. 44 n/a n/a 750 10.7 32.4 7.68 62 125 50 5** 24 test ckt. 1 100f 5 none yes , cf. fig. 44 n/a n/a 1000 9.09 32.4 7.68 65 130 50 *for all conditions: c inh input capacitance is 10f 3, per channel (v in0 , v in1 ). c inl bulk input capacitance of 150f is optional if v in has very low input impedance. **5v out supported on v out1 channel output, only. v out0 channel supported range of output voltage regulation is limited to 4v out , max. exception for dual phase single output operation shown in figure 42. a pplica t ions i n f or m a t ion - dera t ing c urves 4676fb for more information www.linear.com/LTM4676 ltm 4676
64 figure 20. 5v to 1.8v derating curve, no heat sink figure 21. 12v to 1.8v derating curve, no heat sink figure 22. 24v to 1.8v derating curve, no heat sink applications information- derating curves ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 20 22 24 26 14 40 50 60 70 4676 f20 4 16 18 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 20 22 24 26 14 40 50 60 70 4676 f21 4 16 18 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 20 22 24 26 14 40 50 60 70 4676 f22 4 16 18 12 80 120 90 100 110 400lfm 200lfm 0lfm figure 14. 5v to 1v derating curve, no heat sink figure 15. 12v to 1v derating curve, no heat sink figure 16. 24v to 1v derating curve, no heat sink figure 18. 12v to 1v derating curve, bga heat sink figure 17. 5v to 1v derating curve, bga heat sink figure 19. 24v to 1v derating curve, bga heat sink ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 20 22 24 26 14 40 50 60 70 4676 f14 4 16 18 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 20 22 24 26 14 40 50 60 70 4676 f15 4 16 18 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 20 22 24 26 14 40 50 60 70 4676 f16 4 16 18 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 20 22 24 26 14 40 50 60 70 4676 f17 4 16 18 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 20 22 24 26 14 40 50 60 70 4676 f18 4 16 18 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 20 22 24 26 14 40 50 60 70 4676 f19 4 16 18 12 80 120 90 100 110 400lfm 200lfm 0lfm 4676fb for more information www.linear.com/LTM4676 ltm 4676
65 figure 24. 12v to 1.8v derating curve, with heat sink figure 23. 5v to 1.8v derating curve, with heat sink figure 25. 24v to 1.8v derating curve, with heat sink figure 27. 12v to 3.3v derating curve, no heat sink figure 26. 5 v to 3.3 v derating curve, no heat sink figure 28. 24v to 3.3v derating curve, with heat sink figure 29. 5v to 3.3v derating curve, with heat sink figure 30. 12v to 3.3v derating curve, with heat sink figure 31. 24v to 3.3v derating curve, with heat sink applications information- derating curves ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 20 22 24 26 14 40 50 60 70 4676 f23 4 16 18 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 20 22 24 26 14 40 50 60 70 4676 f24 4 16 18 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 20 22 24 26 14 40 50 60 70 4676 f25 4 16 18 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 20 22 24 26 14 40 50 60 70 4676 f26 4 16 18 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 20 22 24 26 14 40 50 60 70 4676 f27 4 16 18 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 20 22 24 26 14 40 50 60 70 4676 f28 4 16 18 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 20 22 24 26 14 40 50 60 70 4676 f29 4 16 18 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 20 22 24 26 14 40 50 60 70 4676 f30 4 16 18 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 20 22 24 26 14 40 50 60 70 4676 f31 4 16 18 12 80 120 90 100 110 400lfm 200lfm 0lfm 4676fb for more information www.linear.com/LTM4676 ltm 4676
66 a pplica t ions i n f or m a t ion emi p erformance the sw n pin provides access to the midpoint of the power mosfets in LTM4676s power stages. connecting an optional series rc network from sw n to gnd can dampen high frequency (~30 mhz+) switch node ringing caused by parasitic inductances and capacitances in the switched-current paths. the rc network is called a snubber circuit because it dampens (or snubs) the resonance of the parasitics, at the expense of higher power loss. to use a snubber, choose first how much power to allocate to the task and how much pcb real estate is available to implement the snubber. for example, if pcb space al - lows a low inductance 1 w resistor to be usedderated conser vatively to 600mw (p snub )then the capacitor in the snubber network (c sw ) is computed by: c sw = p snub v in n (max) 2 ? f sw where v inn (max) is the maximum input voltage that the input to the power stage ( v inn ) will see in the application, and f sw is the dc/dc converters switching frequency of operation. c sw should be npo, c0g or x7r-type (or better) material. the snubber resistor (r sw ) value is then given by: r sw = 5nh c sw the snubber resistor should be low esl and capable of withstanding the pulsed currents present in snubber cir- cuits. a value between 0.7 and 4.2 is normal. for ease of snubber implementation, integrated 2.2nf snubber capacitors connect to each of the LTM4676s channel switch nodes via a low inductance path. the electrically floating ends of these snubber capacitors are made available on the snub n pins of the LTM4676. us- ing the aforementioned guidance on snubber selection, a properly sized snubber resistor can be conveniently connected directly between snub n and gnd. emi performance of LTM4676 ( on dc1811) with and with- out a snubber is compared and contrasted in figures?32 and 33. the snubber resistors applied to the snub n pins reduce emi signal amplitude by several dbv/m. figure 32. radiated emissions scan of LTM4676 producing 1v out at 26a, from 12v in . dc1811 hardware with outputs paralleled. no snubbers applied. f sw = 350khz. measured in a 10m chamber. peak detect method figure 33. radiated emissions scan of LTM4676 producing 1v out at 26a, from 12v in . dc1811 hardware with outputs paralleled. 1 (1/4w rated) snubber resistors applied from snub n to gnd. f sw = 350khz. measured in a 10m chamber. peak detect method frequency (mhz) 30 ?10 signal amplitude (db v/m) 0 10 30 40 50 70 4676 f33 20 60 422.4 1010 226.2 618.6 814.8 frequency (mhz) 30 ?10 signal amplitude (db v/m) 0 10 30 40 50 70 4676 f32 20 60 422.4 1010 226.2 618.6 814.8 4676fb for more information www.linear.com/LTM4676 ltm 4676
67 a pplica t ions i n f or m a t ion s afety c onsiderations the LTM4676 modules do not provide galvanic isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. the fuse or circuit breaker should be selected to limit the current to the regulator during overvoltage in case of an internal top mosfet fault. if the internal top mosfet fails, then turning it off will not resolve the overvoltage, thus the internal bottom mosfet will turn on indefinitely trying to protect the load. under this fault condition, the input volt - age will source very large currents to ground through the failed internal top mosfet and enabled internal bottom mosfet. this can cause excessive heat and board dam - age depending on how much power the input voltage can deliver to this system. a fuse or circuit breaker can be used as a secondary fault protector in this situation. the device does support over current and overtemperature protection. l ayout c hecklist /e xample the high integration of LTM4676 makes the pcb board layout very simple and easy. however, to optimize its electrical and thermal performance, some layout consid- erations are still necessary. ? use large pcb copper areas for high current paths, including v inn , gnd and v outn . it helps to minimize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capaci - tors next to the v inn , gnd and v outn pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the module. ? to minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. ? do not put vias directly on pads, unless they are capped or plated over. ? use a separate sgnd copper plane for components connected to signal pins. connect sgnd to gnd at channel 1s load gnd sense point. ? for parallel modules, tie the v outn , v osns0 + /v osns C and/ or v osns1 /sgnd voltage-sense differential pair lines, run n , gpio n , comp n a , sync and share_clk pins togetheras shown in figure 39. ? bring out test points on the signal pins for monitoring. figure 34 gives a good example of the recommended layout. sgnd 12 11 10 9 8 7 6 5 c out0 gnd c out1 c in1 c in0 v in0 v in1 gnd gnd 4 3 2 1 a b c d e f g cntrl v out1 4676 f34a v out0 h j k l m figure 34. recommended pcb layout package top view v in0 v in1 v out0 v out1 a 12 11 10 9 8 7 6 5 4 3 2 1 b c d e f g h j k l m gnd gnd gnd gnd gnd 4676fb for more information www.linear.com/LTM4676 ltm 4676
68 typical a pplica t ions c inh 22f 3 c inl 220f 10k 7 v in 4.5v to 5.75v pwm clock synch. time base synch. ? slave address = 1001010_r/w (0x4a) ? 350khz switching frequency ? no gui con?guration and no part-speci?c programming required except: vin_off < vin_uv_warn_limit < vin_on < 4.3v in multi-module systems, con?guring rail_address is recommended c out 100f 14 v out , 1.5v adjustable up to 26a v out0 tsns 0a tsns 0b i sns0a + i sns0b + i sns0a ? i sns0b ? v osns0 + v osns0 ? v out1 tsns 1a tsns 1b i sns1a + i sns1b + i sns1a ? i sns1b ? v osns1 sgnd v in0 v in1 sv in v dd33 load scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk v out0cfg v trim0cfg v out1cfg v trim1cfg intv cc v dd25 sw 0 sw 1 snub 0 snub 1 comp 0a comp 0b comp 1a comp 1b gnd wp 10.7k 1% 50ppm/c 22.6k 1% 50ppm/c LTM4676 4676 f35 + 2.1k 1% 50ppm/c smbus interface with pmbus command set on/off control, fault management, power sequencing f swphcfg asel figure 35. 26a, 1.5v output dc/dc module regulator with i 2 c/smbus/pmbus serial interface (36a) 5v in , figure 35 circuit (36b) 12v in , figure 35 circuit with intv cc open and v out commanded to 1v total output current (a) 0 channel output current (a) 12 12 4676 f36a 6 2 4 8 16 0 ?2 14 10 i out0 i out1 8 4 20 24 28 total output current (a) 0 channel output current (a) 12 12 4676 f36b 6 2 4 8 16 0 ?2 14 10 i out0 i out1 8 4 20 24 28 figure 36. current sharing performance of the LTM4676's channels 4676fb for more information www.linear.com/LTM4676 ltm 4676
69 typical a pplica t ions figure 37. 13a, 1.2v and 2.5v outputs generated from 3.3v power input and providing i 2 c/smbus/pmbus serial interface figure 38. output voltage margining, figure 37 circuit v out1 , 2.5v adjustable up to 13a c inh 22f 3 c inl 220f 10k 9 3.3v in nominal 5v low power bias <100ma pwm clock synch. time base synch. ? slave address = 1001111_r/w (0x4f) ? 350khz switching frequency ? no gui con?guration and no part-speci?c programming required except: vin_off < vin_uv_warn_limit < vin_on < 4.5v in multi-module systems, con?guring rail_address is recommended c out0 100f 7 c out1 100f 7 v out0 , 1.2v adjustable up to 13a v out0 tsns 0a tsns 0b i sns0a + i sns0b + i sns0a ? i sns0b ? v osns0 + v osns0 ? v out1 tsns 1a tsns 1b i sns1a + i sns1b + i sns1a ? i sns1b ? v osns1 sgnd v in0 v in1 sv in v dd33 load 0 scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk v out0cfg v trim0cfg v out1cfg v trim1cfg intv cc v dd25 sw 0 sw 1 snub 0 snub 1 comp 0a comp 0b comp 1a comp 1b gnd wp 22.6k 1% 50ppm/c 3.24k 1% 50ppm/c LTM4676 4676 f37 + 10.7k 1% 50ppm/c smbus interface with pmbus command set on/off control, fault management, power sequencing load 1 f swphcfg asel (38a) pmbus operation (reg. 0x01): 0x80 0xa8 (margin high) (38c) pmbus operation (reg. 0x01): 0x80 0x98 (margin low) (38b) pmbus operation (reg. 0x01): 0xa8 0x80 (margin off) (38d) pmbus operation (reg. 0x01): 0x98 0x80 (margin off) v out1 50mv/div v out0 50mv/div scl 5v/div sda 5v/div 4ms/div 4676 f38a v out1 50mv/div v out0 50mv/div scl 5v/div sda 5v/div 4ms/div 4676 f38b v out1 50mv/div v out0 50mv/div scl 5v/div sda 5v/div 4ms/div 4676 f38c v out1 50mv/div v out0 50mv/div scl 5v/div sda 5v/div 4ms/div 4676 f38d 4676fb for more information www.linear.com/LTM4676 ltm 4676
70 typical a pplica t ions figure 39. four paralleled LTM4676 producing 1v out at up to 100a. integrated power system management features accessible over 2-wire i 2 c/smbus/pmbus serial interface. for evaluation and more information, see demo boards dc1989, dc1989a-c c in1 10f 4 c in5 150f 10k 7 v in 5.75v to 16v pwm clock synch. time base synch. c out(mlcc) 100f 10 c out(bulk) 330f 10 v out , 1v adjustable up to 100a v out0 tsns 0a tsns 0b i sns0a + i sns0b + i sns0a ? i sns0b ? v osns0 + v osns0 ? v ino v in1 sv in v dd33 load scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk asel f swphcfg v out0cfg v trim0cfg v out1cfg v trim1cfg intv cc v dd25 sw 0 sw 1 snub 0 snub 1 comp 0a comp 0b comp 1a comp 1b gnd wp 22.6k 1% 50ppm/c u1 LTM4676 + smbus interface with pmbus command set u1: slave address = 1000000_r/w (0x40) u2: slave address = 1000001_r/w (0x41) u3: slave address = 1000010_r/w (0x42) u4: slave address = 1000011_r/w (0x43) 350khz switching frequency with interleaving no gui con?guration and no part-speci?c programming required in multi-module systems, con?guring rail_address is recommended on/off control, fault management, power sequencing c in2 10f 4 v out0 tsns 0a tsns 0b i sns0a + i sns0b + i sns0a ? i sns0b ? v osns0 + v osns0 ? v ino v in1 sv in v dd33 scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk f swphcfg v out0cfg v trim0cfg v out1cfg v trim1cfg intv cc v dd25 sw 0 sw 1 snub 0 snub 1 comp 0a comp 0b comp 1a comp 1b gnd wp 1.65k 1% 50ppm/c 787 1% 50ppm/c u2 LTM4676 asel c in3 10f 4 v out0 tsns 0a tsns 0b i sns0a + i sns0b + i sns0a ? i sns0b ? v osns0 + v osns0 ? v ino v in1 sv in v dd33 scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk f swphcfg v out0cfg v trim0cfg v out1cfg v trim1cfg intv cc v dd25 sw 0 sw 1 snub 0 snub 1 comp 0a comp 0b comp 1a comp 1b gnd wp 3.24k 1% 50ppm/c 1.65k 1% 50ppm/c u3 LTM4676 asel c in4 10f 4 v out0 tsns 0a tsns 0b i sns0a + i sns0b + i sns0a ? i sns0b ? v osns0 + v osns0 ? v ino v in1 sv in v dd33 scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk f swphcfg v out0cfg v trim0cfg v out1cfg v trim1cfg intv cc v dd25 sw 0 sw 1 snub 0 snub 1 comp 0a comp 0b comp 1a comp 1b gnd wp 1.21k 1% 50ppm/c 4676 f39 c thp 220pf c th 3.3nf r th 1.65k u4 LTM4676 asel v out1 tsns 1a tsns 1b i sns1a + i sns1b + i sns1a ? i sns1b ? v osns1 sgnd v out1 tsns 1a tsns 1b i sns1a + i sns1b + i sns1a ? i sns1b ? v osns1 sgnd v out1 tsns 1a tsns 1b i sns1a + i sns1b + i sns1a ? i sns1b ? v osns1 sgnd v out1 tsns 1a tsns 1b i sns1a + i sns1b + i sns1a ? i sns1b ? v osns1 sgnd 4676fb for more information www.linear.com/LTM4676 ltm 4676
71 typical a pplica t ions figure 40. one LTM4676 operating in parallel with 3xltm4620a or 3xltm4630 (see demo boards dc2106a-a, dc2106a-b) producing 1v out at up to 100a ~ 130a. power system management features accessible through LTM4676. see figure 41 c in1 10f 4 c in5 150f 10k 6 12v in 20% c in2 10f 4 c out(mlcc) 100f 20 c out(bulk) 470f 10 v out , 1v adjustable up to 100a~130a v out0 tsns 0a tsns 0b i sns0a + i sns0b + i sns0a ? i sns0b ? v osns0 + v osns0 ? v ino v in1 sv in v dd33 load scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk asel f swphcfg v out0cfg v trim0cfg v out1cfg v trim1cfg intv cc v dd25 sw 0 sw 1 snub 0 snub 1 comp 0a comp 0b comp 1a comp 1b gnd wp u1 LTM4676 u2* + v out1 tsns 1a tsns 1b i sns1a + i sns1b + i sns1a ? i sns1b ? v osns1 sgnd pwm clock synch. time base synch. smbus interface with pmbus command set on/off control, fault management, power sequencing r th * c th * c intvcc2 4.7f u1: slave address = 1000000_r/w (0x40) 500khz switching frequency with interleaving no gui configuration and no part-specific programming required except: iout_oc_warn_limit n =18a mfr_gpio_response n = 0x00 in multi-module systems, configuring rail_address is recommended r clk 200 m1 2n7002a 1.2k 1% 50ppm/c 6.34k 1% 50ppm/c r temp2 121k r vfb 8.25k r fset2 121k r div1 * r div2 * c in3 10f 4 c in4 10f 4 ? + u5a 1/2 lt1801 v in temp extv cc phasmd run1 run2 track1 track2 pgood1 v out1 v outs1 v fb1 v out2 v outs2 v fb2 diffp diffn diffout mode_pllin sw1 sw2 intv cc clkout sgnd gnd pgood2 comp1 comp2 f set u3* c intvcc3 4.7f r temp3 121k r fset3 121k temp extv cc phasmd run1 run2 track1 track2 pgood1 v out1 v outs1 v fb1 v out2 v outs2 v fb2 diffp diffn diffout mode_pllin sw1 sw2 intv cc clkout sgnd gnd pgood2 comp1 comp2 f set u4* c intvcc4 4.7f r temp4 121k r fset4 121k temp extv cc phasmd run1 run2 track1 track2 pgood1 v out1 v outs1 v fb1 v out2 v outs2 v fb2 diffp diffn diffout mode_pllin sw1 sw2 intv cc clkout sgnd gnd pgood2 4676 f40 comp1 comp2 f set ? + u5b 1/2 lt1801 demo board dc2106a-a dc2106a-b output current up to 100a up to 130a u2, u3, u4 ltm4620a ltm4630 r div1 23.2k 20k r div2 76.8k 80.6k r th 6.98k 7.15k c th 4.7nf 2.2nf *stuffing options 4676fb for more information www.linear.com/LTM4676 ltm 4676
72 typical a pplica t ions figure 41a. LTM4676 paralleled with 3x ltm4620a (up to 100a output) figure 41b. LTM4676 paralleled with 3x ltm4630 (up to 130a output) figure 41. current sharing performance of figure 40 circuit at 12v in total output current (a) 0 channel output current (a) 6 8 10 9080 4676 f41a 4 2 ?2 20 40 60 10 100 30 50 70 0 14 12 u1-LTM4676-i out0 u1-LTM4676-i out1 u2-ltm4620a-i out1 u2-ltm4620a-i out2 u3-ltm4620a-i out1 u3-ltm4620a-i out2 u4-ltm4620a-i out1 u4-ltm4620a-i out2 total output current (a) 0 channel output current (a) 18 60 4676 f41b 9 3 20 40 80 0 ?3 21 15 12 6 100 120 140 u1-LTM4676-i out0 u1-LTM4676-i out1 u2-ltm4630-i out1 u2-ltm4630-i out2 u3-ltm4630-i out1 u3-ltm4630-i out2 u4-ltm4630-i out1 u4-ltm4630-i out2 4676fb for more information www.linear.com/LTM4676 ltm 4676
73 typical a pplica t ions c inh 22f 3 c inl 220f 10k 7 v in 5.75v to 26.5v pwm clock synch. time base synch. ? slave address = 1000101_r/w (0x45) ? 750khz switching frequency ? no gui con?guration and no part-speci?c programming required in multi-module systems, con?guring rail_address is recommended ? in order to operate channel 0 at 5v out , a resistor-divider network (r div1 and r div2 ) is used to keep v osns0 within its valid common mode range ? as a result of the 2:1 feedback resistor-divider network (r div1 and r div2 ), all LTM4676 channel 0 v out -related parameters, thresholds, and v out telemetry are commanded and readback as one-half of what is desired or present at the load (explicitly: 5v out at the load corresponds to a vout_command 0 setting of 2.5v and a read_vout 0 result of 2.5v) ? in this con?guration, the output current reading of channel 0 reads lower than normal and is invalid (and similarly, for related telemetry: channel 0 output power and input current readback). all channel 1 telemetry, however, remains valid c out 100f 10 v out , 5v adjustable up to 26a optional: installing u2 away from heat sources allows intv cc ldo losses normally incurred by the LTM4676 to be dissipated instead by the lt3060. thermal-derating can thus be improved v out0 tsns 0a tsns 0b i sns0a + i sns0b + i sns0a ? i sns0b ? v osns0 + v osns0 ? v out1 tsns 1a tsns 1b i sns1a + i sns1b + i sns1a ? i sns1b ? v osns1 sgnd v in0 v in1 sv in v dd33 load r div1 249 0.1% r div2 249 0.1% scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk v out0cfg v trim0cfg v out1cfg v trim1cfg intv cc v dd25 sw 0 sw 1 snub 0 snub 1 comp 0a comp 0b comp 1a comp 1b gnd wp 4.22k 1% 50ppm/c 5.36k 1% 50ppm/c u1 LTM4676 4676 f42 + 32.4k 1% 50ppm/c 7.68k 1% 50ppm/c smbus interface with pmbus command set on/off control, fault management, power sequencing f swphcfg asel in r set1 13.3k r set2 1.62k out shdn adj u2 lt3060 gnd ref/byp figure 42. 26a, 5v output dc/dc module regulator with serial interface figure 43. output derating curve of figure 42 circuit tested on dc1811a, 12v in , no heat sink ambient temperature (c) 30 40 0 maximum load current (a) 2 6 8 10 20 22 24 26 14 50 70 4676 f43 4 16 18 12 90 120110 60 80 100 400lfm, with u2, r set1 and r set2 installed: ja = 6.2c/w 200lfm, with u2, r set1 and r set2 installed: ja = 7.9c/w 400lfm, with u2, r set1 and r set2 not used: ja = 7.3c/w 200lfm, with u2, r set1 and r set2 not used: ja = 8.9c/w 4676fb for more information www.linear.com/LTM4676 ltm 4676
74 p ackage descrip t ion package row and column labeling m ay vary among module products. review each package layout carefully. table 21. LTM4676 bga pinout pin id function pin id function pin id function pin id function pin id function pin id function a1 v out0 b1 v out0 c1 v out0 d1 v out0 e1 i sns0b C f1 i sns0b + a2 v out0 b2 v out0 c2 v out0 d2 v out0 e2 i sns0a C f2 i sns0a + a3 v out0 b3 v out0 c3 v out0 d3 v out0 e3 gnd f3 gnd a4 gnd b4 gnd c4 gnd d4 gnd e4 gpio 0 f4 gpio 1 a5 snub 0 b5 gnd c5 tsns 0b d5 tsns 0a e5 alert f5 run 0 a6 gnd b6 gnd c6 gnd d6 sda e6 scl f6 run 1 a7 gnd b7 gnd c7 gnd d7 gnd e7 sync f7 sgnd a8 gnd b8 gnd c8 gnd d8 comp 0b e8 comp 0a f8 sgnd a9 gnd b9 gnd c9 gnd d9 v osns0 + e9 v osns0 C f9 intv cc a10 gnd b10 sw 0 c10 dnc d10 v orb0 + e10 v orb0 C f10 gnd a11 v in0 b11 v in0 c11 v in0 d11 v in0 e11 dnc f11 sv in a12 v in0 b12 v in0 c12 v in0 d12 v in0 e12 v in0 f12 sv in pin id function pin id function pin id function pin id function pin id function pin id function g1 i sns1b C h1 i sns1b + j1 v out1 k1 v out1 l1 v out1 m1 v out1 g2 i sns1a C h2 i sns1a + j2 v out1 k2 v out1 l2 v out1 m2 v out1 g3 gnd h3 gnd j3 v out1 k3 v out1 l3 v out1 m3 v out1 g4 asel h4 f swphcfg j4 gnd k4 gnd l4 gnd m4 gnd g5 v out0cfg h5 v trim0cfg j5 tsns 1a k5 tsns 1b l5 gnd m5 snub 1 g6 v out1cfg h6 v trim1cfg j6 v dd25 k6 wp l6 gnd m6 gnd g7 sgnd h7 share_clk j7 v dd33 k7 gnd l7 gnd m7 gnd g8 sgnd h8 comp 1a j8 comp 1b k8 gnd l8 gnd m8 gnd g9 intv cc h9 v osns1 j9 v orb1 k9 gnd l9 gnd m9 gnd g10 gnd h10 gnd j10 gnd k10 dnc l10 sw1 m10 gnd g11 gnd h11 dnc j11 v in1 k11 v in1 l11 v in1 m11 v in1 g12 gnd h12 v in1 j12 v in1 k12 v in1 l12 v in1 m12 v in1 4676fb for more information www.linear.com/LTM4676 ltm 4676
75 p ackage descrip t ion p ackage p ho t ograph v out0 v out0 i sns0b ? i sns1b ? i sns1a ? i sns1b + i sns1a + f swphcfg i sns0a ? gpio 0 gpio 1 i sns0b + i sns0a + 1 2 3 4 5 6 7 top view 8 9 10 11 12 m l k j h g f e d c b a v in0 v in0 gnd gnd gnd sw 0 gnd snub 0 tsns 0b tsns 0a run0 alert dnc gnd comp 0b v osns0 + v orb0 ? dnc sv in sv in v orb0 + v osns0 ? comp 0a sync sda scl run 1 sgnd intv cc gnd gnd gnd asel v out0cfg v trim0cfg v trim1cfg share_clk comp 1a v osns1 v out1cfg gnd gnd gnd dnc v out1 tsns 1a tsns 1b wp dnc sw 1 v dd25 v dd33 comp 1b v orb1 v out1 snub 1 v in1 v in1 4676fb for more information www.linear.com/LTM4676 ltm 4676
76 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. bga package 144-lead (16mm 16mm 5.01mm) (reference ltc dwg # 05-08-1920 rev b) package top view 4 pin ?a1? corner x y aaa z aaa z package bottom view 3 see notes d e b e e b f g bga 144 0213 rev b tray pin 1 bevel package in tray loading orientation component pin ?a1? ltmxxxxxx module detail a pin 1 11 10 9 8 7 6 5 4 3 2 12 1 a b c d e f g h k j l m suggested pcb layout top view 0.0000 0.0000 0.630 0.025 ? 144x 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 detail a ?b (144 places) a detail b package side view z m x yzddd m zeee a2 detail b substrate a1 b1 ccc z mold cap symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 4.81 0.50 4.31 0.60 0.60 0.36 3.95 nom 5.01 0.60 4.41 0.75 0.63 16.00 16.00 1.27 13.97 13.97 0.41 4.00 max 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 notes dimensions total number of balls: 144 // bbb z z h2 h1 notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 6. solder ball composition is 96.5% sn/3.0% ag/0.5% cu 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature 7 package row and column labeling may vary among module products. review each package layout carefully ! 7 see notes 4676fb for more information www.linear.com/LTM4676 ltm 4676
77 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 12/13 added video tech clip link corrected figure numbers in tables 15, 16 and 17 1 61 b 2/14 added snpb bga option updated part number in figure 40 1, 3 71 4676fb for more information www.linear.com/LTM4676 ltm 4676
78 ? linear technology corporation 2013 lt 0214 rev b ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTM4676 r ela t e d p ar t s typical a pplica t ion figure 44. 13a, 1v and 13a, 1.8v output dc/dc module regulator with serial interface v out1 , 1.8v adjustable up to 13a c inh 22f 3 c inl 220f 10k 9 v in 5.75v to 26.5v pwm clock synch. time base synch. ? slave address = 1001111_r/w (0x4f) ? switching frequency: 350khz ? no gui con?guration and no part speci?c programming required in multi-module systems, con?guring rail_address is recommended c out0 100f 7 c out1 100f 7 v out0 , 1.0v adjustable up to 13a v out0 tsns 0a tsns 0b i sns0a + i sns0b + i sns0a ? i sns0b ? v osns0 + v osns0 ? v out1 tsns 1a tsns 1b i sns1a + i sns1b + i sns1a ? i sns1b ? v osns1 sgnd v in0 v in1 sv in v dd33 load 0 scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk asel f swphcfg v out0cfg v trim0cfg v out1cfg v trim1cfg intv cc v dd25 sw 0 sw 1 snub 0 snub 1 comp 0a comp 0b comp 1a comp 1b gnd wp 6.34k 1% 50ppm/c LTM4676 4676 f44 + 22.6k 1% 50ppm/c smbus interface with pmbus command set on/off control, fault management, power sequencing load 1 design r esources subject description module design and manufacturing resources design: ? selector guides ? demo boards and gerber files ? free simulation tools manufacturing: ? quick start guide ? pcb design, assembly and manufacturing guidelines ? package and board level reliability module regulator products sear ch 1. sort table of products by parameters and download the result as a spread sheet. 2. search using the quick power sear ch parametric table. techclip videos quick videos detailing how to bench test electrical and thermal performance of module products. digital power system management linear technologys family of digital power supply management ics are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature eeprom for storing user configurations and fault logging. part number description comments ltm4620a dual 13a or single 26a step-down module regulator 4.5v v in 16v, 0.6v v out 5.3v, 15mm 15mm 4.41mm lga ltm4630 dual 18a or single 36a step-down module regulator 4.5v v in 15v, 0.6v v out 1.8v, 16mm 16mm 4.41mm lga ltm4641 10a module regulator with advanced input and load protection 4.5v v in 38v, 0.6v v out 6v, 15mm 15mm 5.01mm bga ltc3880/ltc3883 dual and single output dc/dc controllers with power system management 0.5% tue 16-bit adc, voltage/current/temperature monitoring and supervision ltc2977/ltc2974 8- and 4-channel pmbus power system managers 0.25% tue 16-bit adc, voltage/temperature monitoring and supervision licensed under u.s. patent 7000125 and other related patents worldwide. 4676fb for more information www.linear.com/LTM4676 ltm 4676

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